Abstract: A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

Abstract: A memory circuit capable of being quickly written in data includes a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. Each segment of the plurality of segments includes a plurality of bit line groups, and each bit line group of the plurality of bit line groups corresponds to a pre-charge line. When a predetermined signal is enabled, a potential is written into memory cells of the each segment corresponding to the each bit line group through the pre-charge line and the each bit line group.

Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: Embodiments including systems, methods, and apparatuses associated with reordering data retrieved from a dynamic random access memory (DRAM). A memory controller may be configured to receive an instruction from a central processing unit (CPU) and, based on the instruction, retrieve a sequential data from a DRAM. The memory controller may then be configured to reorder the sequential data and place the reordered data in one or more locations of a vector register file.

Abstract: A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: A power-up initial circuit includes a power-up control unit, a first switch and a second switch. The power-up control unit is used for receiving a high voltage start-up signal, and generating a first power-up control signal. The first switch has a first terminal for receiving an external voltage, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal. The second switch has a first terminal coupled to the third terminal of the first switch, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal for coupling to a high voltage generator.

Abstract: A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

Abstract: A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage.

Abstract: A method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration includes supplying power to the memory circuit, utilizing the impedance matching circuit to perform the initial calibration on the memory circuit, the memory circuit exiting the initial calibration, the memory circuit entering a driving mode, the memory circuit exiting the driving mode every a predetermined interval, utilizing the impedance matching circuit to perform the full time refresh mode calibration on the memory circuit according to a refresh command, an output voltage detection circuit determining a level of an output voltage of the memory circuit, and performing a corresponding operation according to a determination result generated by the output voltage detection circuit.

Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.

Abstract: A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle.

Abstract: A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.

Abstract: A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current.

Abstract: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.

Abstract: A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.

Abstract: A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.