Patents by Inventor Chun-Wen Paul Huang
Chun-Wen Paul Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10869362Abstract: In some embodiments, a wireless local area network (WLAN) front-end can be implemented on a semiconductor die having a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to support the transmit and receive operations.Type: GrantFiled: December 4, 2018Date of Patent: December 15, 2020Assignee: Skyworks Solutions, Inc.Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty, Michael Joseph McPartlin
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Publication number: 20190386619Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.Type: ApplicationFiled: December 18, 2018Publication date: December 19, 2019Inventors: Chun-Wen Paul HUANG, Lui LAM, Mark M. DOHERTY
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Publication number: 20190182894Abstract: In some embodiments, a wireless local area network (WLAN) front-end can be implemented on a semiconductor die having a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to support the transmit and receive operations.Type: ApplicationFiled: December 4, 2018Publication date: June 13, 2019Inventors: Chun-Wen Paul HUANG, Lui LAM, Mark M. DOHERTY, Michael Joseph MCPARTLIN
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Patent number: 10158333Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.Type: GrantFiled: April 17, 2017Date of Patent: December 18, 2018Assignee: Skyworks Solutions, Inc.Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty
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Patent number: 10149347Abstract: Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.Type: GrantFiled: January 6, 2016Date of Patent: December 4, 2018Assignee: Skyworks Solutions, Inc.Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty, Michael Joseph McPartlin
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Publication number: 20170338776Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.Type: ApplicationFiled: April 17, 2017Publication date: November 23, 2017Inventors: Chun-Wen Paul HUANG, Lui LAM, Mark M. DOHERTY
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Patent number: 9628029Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.Type: GrantFiled: December 30, 2014Date of Patent: April 18, 2017Assignee: Skyworks Solutions, Inc.Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty
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Publication number: 20160227603Abstract: Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.Type: ApplicationFiled: January 6, 2016Publication date: August 4, 2016Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty, Michael Joseph McPartlin
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Publication number: 20150303883Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.Type: ApplicationFiled: December 30, 2014Publication date: October 22, 2015Inventors: Chun-Wen Paul HUANG, Lui LAM, Mark M. DOHERTY
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Patent number: 8824983Abstract: A system and method are provided for reducing dynamic EVM of an integrated circuit power amplifier (PA) used for RF communication. In a multistage PA, the largest amplification stage is biased with a high amplitude current pulse upon receipt of a Tx enable, before receipt of the RF signal data burst. The high amplitude current pulse causes a large portion of the total ICQ budget of the multistage PA to pass through the largest amplification stage causing the entire integrated circuit to rapidly approach steady-state operating conditions. A smoothing bias current is applied to the largest amplification stage after the pulse decays to compensate for transient bias current levels while standard bias circuitry is still approaching steady-state temperature.Type: GrantFiled: June 28, 2012Date of Patent: September 2, 2014Assignee: SiGe Semiconductor, Inc.Inventors: Mark M. Doherty, Lui Lam, Chun-Wen Paul Huang, Anthony Francis Quaglietta
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Patent number: 8749032Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.Type: GrantFiled: December 1, 2009Date of Patent: June 10, 2014Assignee: SiGe Semiconductor, Inc.Inventors: Mark Doherty, Michael McPartlin, Chun-Wen Paul Huang
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Patent number: 8729949Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided.Type: GrantFiled: May 15, 2013Date of Patent: May 20, 2014Assignee: SiGe Semiconductor, Inc.Inventors: John Jackson Nisbet, Michael Joseph McPartlin, Chun-Wen Paul Huang
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Publication number: 20130260698Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided.Type: ApplicationFiled: May 15, 2013Publication date: October 3, 2013Applicant: SiGe Semiconductor, Inc.Inventors: John Jackson Nisbet, Michael Joseph McPartlin, Chun-Wen Paul Huang
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Patent number: 8476961Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.Type: GrantFiled: January 6, 2012Date of Patent: July 2, 2013Assignee: SiGe Semiconductor, Inc.Inventors: Chun-Wen Paul Huang, Mark Doherty, Philip Michael Antognetti
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Patent number: 8451044Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complementary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output.Type: GrantFiled: June 29, 2009Date of Patent: May 28, 2013Assignee: SiGe Semiconductor, Inc.Inventors: John Nisbet, Michael McPartlin, Chun-Wen Paul Huang
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Publication number: 20130034144Abstract: A system and method are provided for reducing dynamic EVM of an integrated circuit power amplifier (PA) used for RF communication. In a multistage PA, the largest amplification stage is biased with a high amplitude current pulse upon receipt of a Tx enable, before receipt of the RF signal data burst. The high amplitude current pulse causes a large portion of the total ICQ budget of the multistage PA to pass through the largest amplification stage causing the entire integrated circuit to rapidly approach steady-state operating conditions. A smoothing bias current is applied to the largest amplification stage after the pulse decays to compensate for transient bias current levels while standard bias circuitry is still approaching steady-state temperature.Type: ApplicationFiled: June 28, 2012Publication date: February 7, 2013Inventors: Mark Doherty, Lui (Ray) Lam, Chun-Wen Paul Huang
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Publication number: 20120202438Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.Type: ApplicationFiled: January 6, 2012Publication date: August 9, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Chun-Wen Paul Huang, Mark Doherty, Philip Michael Antognetti
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Patent number: 8093940Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.Type: GrantFiled: April 16, 2010Date of Patent: January 10, 2012Assignee: SiGe Semiconductor Inc.Inventors: Chun-Wen Paul Huang, Mark Doherty, Philip Michael Antognetti
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Publication number: 20110254614Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: SiGe Semiconductor Inc.Inventors: Chun-Wen Paul Huang, Mark Doherty, Philip Michael Antognetti
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Publication number: 20110128078Abstract: A system and method are provided for reducing dynamic EVM of an integrated circuit power amplifier (PA) used for RF communication. In a multistage PA, the largest amplification stage is biased with a high amplitude current pulse upon receipt of a Tx enable, before receipt of the RF signal data burst. The high amplitude current pulse causes a large portion of the total ICQ budget of the multistage PA to pass through the largest amplification stage causing the entire integrated circuit to rapidly approach steady-state operating conditions. A smoothing bias current is applied to the largest amplification stage after the pulse decays to compensate for transient bias current levels while standard bias circuitry is still approaching steady-state temperature.Type: ApplicationFiled: December 2, 2009Publication date: June 2, 2011Applicant: SiGe Semiconductor Inc.Inventors: Mark Doherty, Lui (Ray) Lam, Chun-Wen Paul Huang