Patents by Inventor Chun Won Byun
Chun Won Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810522Abstract: A pixel circuit driving method of controlling an operation of a light-emitting element provided in a pixel of a display panel may comprise: applying pulse amplitude modulation (PAM) signals having a plurality of levels to a first terminal of a first transistor having a second terminal connected to a control terminal of a second transistor configured to drive the light-emitting element with a current according to a gray scale required for the light-emitting element; and applying a PAM signal of any one level selected from the PAM signals to the control terminal of the second transistor during each sub-frame time corresponding to a turn-on time of the first transistor controlled by a pulse width modulation (PWM) signal having a plurality of sub-frames in a single frame according to the gray scale.Type: GrantFiled: September 8, 2022Date of Patent: November 7, 2023Assignees: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Chun Won Byun, Chan Mo Kang, Nam Sung Cho, Byong Deok Choi, Yong Duck Kim
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Publication number: 20230290306Abstract: A pixel circuit may comprise: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to a light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied.Type: ApplicationFiled: March 9, 2023Publication date: September 14, 2023Applicants: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Chun Won BYUN, Chan Mo KANG, Nam Sung CHO, Byong Deok CHOI, Yong Duck KIM
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Publication number: 20230230550Abstract: A pixel circuit driving method of controlling an operation of a light-emitting element provided in a pixel of a display panel may comprise: applying pulse amplitude modulation (PAM) signals having a plurality of levels to a first terminal of a first transistor having a second terminal connected to a control terminal of a second transistor configured to drive the light-emitting element with a current according to a gray scale required for the light-emitting element; and applying a PAM signal of any one level selected from the PAM signals to the control terminal of the second transistor during each sub-frame time corresponding to a turn-on time of the first transistor controlled by a pulse width modulation (PWM) signal having a plurality of sub-frames in a single frame according to the gray scale.Type: ApplicationFiled: September 8, 2022Publication date: July 20, 2023Applicants: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Chun Won BYUN, Chan Mo KANG, Nam Sung CHO, Byong Deok CHOI, Yong Duck KIM
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Patent number: 9524992Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: GrantFiled: October 5, 2015Date of Patent: December 20, 2016Assignee: Samsung Display Co., Ltd.Inventors: Hye Young Ryu, Hee Jun Byeon, Woo Geun Lee, Kap Soo Yoon, Yoon Ho Kim, Chun Won Byun
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Publication number: 20160027805Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Hye Young RYU, Hee Jun BYEON, Woo Geun LEE, Kap Soo YOON, Yoon Ho KIM, Chun Won BYUN
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Patent number: 9153600Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: GrantFiled: September 14, 2012Date of Patent: October 6, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hye Young Ryu, Hee Jun Byeon, Woo Geun Lee, Kap Soo Yoon, Yoon Ho Kim, Chun Won Byun
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Publication number: 20150236169Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.Type: ApplicationFiled: May 5, 2015Publication date: August 20, 2015Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBONInventors: Sang Hee PARK, Chi Sun HWANG, Chun Won BYUN, Elvira M.C. FORTUNATO, Rodrigo F.P. MARTINS, Ana R.X. BARROS, Nuno F.O. CORREIA, Pedro M.C. BARQUINHA, Vitor M.L. FIGUEIREDO
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Patent number: 9053937Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.Type: GrantFiled: April 14, 2011Date of Patent: June 9, 2015Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBONInventors: Sang Hee Park, Chi Sun Hwang, Chun Won Byun, Elvira M. C. Fortunato, Rodrigo F. P. Martins, Ana R. X. Barros, Nuno F. O. Correia, Pedro M. C. Barquinha, Vitor M. L. Figueiredo
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Patent number: 8716035Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: GrantFiled: September 10, 2013Date of Patent: May 6, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Chun Won Byun, Shin Hyuk Yang, Sang Hee Park, Soon Won Jung, Seung Youl Kang, Chi Sun Hwang, Byoung Gon Yu
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Publication number: 20140011297Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTEInventors: Sung Min YOON, Chun Won BYUN, Shin Hyuk YANG, Sang Hee PARK, Soon Won JUNG, Seung Youl KANG, Chi Sun HWANG, Byoung Gon YU
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Patent number: 8558295Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: GrantFiled: July 19, 2010Date of Patent: October 15, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Chun Won Byun, Shin Hyuk Yang, Sang Hee Park, Soon Won Jung, Seung Youl Kang, Chi Sun Hwang, Byoung Gon Yu
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Patent number: 8546198Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: March 11, 2013Date of Patent: October 1, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Patent number: 8546199Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: March 11, 2013Date of Patent: October 1, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20130214299Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: ApplicationFiled: September 14, 2012Publication date: August 22, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Hye Young RYU, Hee Jun BYEON, Woo Geun LEE, Kap Soo YOON, Yoon Ho KIM, Chun Won BYUN
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Patent number: 8476106Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.Type: GrantFiled: May 11, 2012Date of Patent: July 2, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Shin Hyuk Yang, Soon Won Jung, Seung Youl Kang, Doo Hee Cho, Chun Won Byun, Chi Sun Hwang, Byoung Gon Yu, Kyoung Ik Cho
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Patent number: 8409935Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: August 21, 2012Date of Patent: April 2, 2013Assignee: Electronics and Telcommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20120315729Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Min Ki RYU, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Patent number: 8269220Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.Type: GrantFiled: September 4, 2009Date of Patent: September 18, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20120225500Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.Type: ApplicationFiled: May 11, 2012Publication date: September 6, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Min YOON, Shin Hyuk Yang, Soon Won Jung, Seung Youl Kang, Doo Hee Cho, Chun Won Byun, Chi Sun Hwang, Byoung Gon Yu, Kyoung Ik Cho
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Patent number: 8198625Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.Type: GrantFiled: September 9, 2009Date of Patent: June 12, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Shin Hyuk Yang, Soon Won Jung, Seung Youl Kang, Doo Hee Cho, Chun Won Byun, Chi Sun Hwang, Byoung Gon Yu, Kyoung Ik Cho