Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Abstract: A core wire includes: an inner conductor; and an insulating layer covering the inner conductor, wherein the insulation layer is made by 3D printing process, the insulating layer includes a first semi-insulating layer and a second semi-insulating layer, each of the first semi-insulating layer and the second semi-insulating layer has a groove that matchingly accommodates the shape of the inner conductor, and the first semi-insulating layer and the second semi-insulating layer are combined together.

Abstract: An auto-configuration method for a time-sensitive networking (TSN) system includes obtaining, by a first OPC UA client module, a TSN configuration of a stream; transmitting, by the first OPC UA client module, the TSN configuration to an OPC UA server module of a centralized user configuration (CUC) in the TSN system; obtaining, by the CUC, a routing information and scheduling of the stream according to the TSN configuration and a network topology; sending, by the first OPC UA client module, a request to the OPC UA server to obtain the routing information and scheduling of the stream; and configuring the routing information and scheduling of the stream to a plurality of end stations in the TSN system after the plurality of end stations are online.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Abstract: A decoration panel includes a first substrate, a first transparent conductive element, a transparent structure, a second substrate, a second transparent conductive element, and a first cholesteric liquid crystal layer. The first transparent conductive element is disposed on the first substrate. The transparent structure is disposed on the first substrate. The second substrate is disposed opposite to the first substrate. The second transparent conductive element is disposed on the second substrate. The first cholesteric liquid crystal layer is disposed between the first transparent conductive element and the second transparent conductive element. A display apparatus is adapted to render a decoration pattern, and the decoration pattern corresponds to the transparent structure. Moreover, a display apparatus including the decoration panel is also provided.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.

Abstract: An electrical connector includes: an insulating body defining a mating space; and a terminal module assembled to the insulating body and having a circuit board and plural mating terminals mounted on the circuit board, wherein: each of the mating terminals has a contact portion extending obliquely backward, a bending portion bent backward from a front end of the contact portion, a connecting portion extending rearward from a rear end of the bending portion, and a mounting portion vertically extending from a rear end of the connecting portion for mounting on the circuit board; and a front end of the circuit board extends forward into the mating space.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

Abstract: An illumination system, a projection device, and a projection control method are provided. The illumination system includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, a first dichroic element, a second dichroic element, and a control unit. The first light-emitting unit includes a first light-emitting element and a second light-emitting element. The control unit is electrically connected to the first light-emitting unit and configured to switch the illumination system between a high-performance mode and a high-chroma mode, wherein when the illumination system is in the high-performance mode, the control unit controls a current ratio of the second light-emitting element to be greater than a current ratio of the first light-emitting element, and when the illumination system is in the high-chroma mode, the control unit controls the current ratio of the second light-emitting element to be less than the current ratio of the first light-emitting element.

Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.

Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, a primary-side trace, a secondary-side trace, and an iron core assembly. The iron core assembly includes an inductor iron core and an iron core. The primary-side trace surrounds the first through hole in a first direction and surrounds the second through hole in a second direction to form an ?-shaped trace. The inductor trace is formed on the primary-side layer board and coupled to the primary-side trace, and two ends of the inductor trace form an input terminal and an output terminal of the planar magnetic component.

Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Abstract: Disclosed herein is a method for determining whether a subject has or is at risk of developing colorectal cancer with an ex vivo biological sample isolated from the subject. The method comprises: determining the levels of at least two target proteins with the aid of mass spectrometry, in which the at least two target proteins are selected from the group consisting of ADAM10, CD59, and TSPAN9; and assessing whether the subject has or is at risk of developing the colorectal cancer based on the levels of the at least two target proteins. The present method may serve as a potential means for diagnosing and predicting the incidence of colorectal cancer, and the subject in need thereof could receive a suitable therapeutic regimen in time in accordance with the diagnostic results produced by the present method.

Abstract: A deflecting plate includes a silicon-on-insulator (SOI) substrate. The SOI substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.