Abstract: The present application discloses an OLED with an improved structure, comprising a reflective anode layer, a transparent cathode layer, an organic light-emitting layer sandwiched between the anode layer and the cathode layer, and a side reflective layer surrounding the organic light-emitting layer and forming a light exiting area together with the anode layer, wherein the light emitted from the light-emitting layer is reflected by both of the anode layer and the side reflective layer, and then leaves from the light exiting area. According to the present disclosure, the lateral light is reflected by the side reflective layer arranged around the organic light-emitting layer, such that the luminescent efficiency of the OLED with said improved structure can be significantly increased.

Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.

Abstract: The present disclosure provides a method for measuring an offset of a sub-pixel in an OLED manufacturing process, including: depositing OLED material onto a display unit in a substrate through a hollow portion of a mask, the display unit including an effective region and a peripheral measuring region at periphery of the effective region, the OLED material forming a plurality of effective sub-pixels within the effective region and forming a plurality of dummy sub-pixels within the peripheral measuring region; and using UV light to excite at least a portion of the dummy sub-pixels of the OLED material to emit light, and measuring the offset of the dummy sub-pixel with respect to a predetermined position of a corresponding light emitting unit located on the substrate.

Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.

Abstract: The present application discloses an OLED with an improved structure, comprising a reflective anode layer, a transparent cathode layer, an organic light-emitting layer sandwiched between the anode layer and the cathode layer, and a side reflective layer surrounding the organic light-emitting layer and forming a light exiting area together with the anode layer, wherein the light emitted from the light-emitting layer is reflected by both of the anode layer and the side reflective layer, and then leaves from the light exiting area. According to the present disclosure, the lateral light is reflected by the side reflective layer arranged around the organic light-emitting layer, such that the luminescent efficiency of the OLED with said improved structure can be significantly increased.

Abstract: Provided is a TFT with an improved gate insulator, having an insulator substrate, a gate layer, a gate insulator layer, a active semiconductor layer, and a source and drain electrode layer, wherein the gate insulator layer includes a first silicon nitride film, a second silicon nitride film disposed on the first silicon nitride film and a third silicon nitride film disposed on the second silicon nitride, and compared to the second silicon nitride film, each of the first silicon nitride film and the third silicon nitride film is much thinner and has a lower content of N—H bond. Also provided is a display including said TFTs. According to the present disclosure, an improved gate insulator layer capable of withstanding higher voltage can be achieved due to the laminated structure and accordingly a TFT with excellent reliability can be formed.

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.