Patents by Inventor Chung-An Tang
Chung-An Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162159Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.Type: ApplicationFiled: January 25, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang WANG, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
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Patent number: 11984668Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.Type: GrantFiled: June 28, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Monsen Liu, Lai Wei Chih, Chung-Hao Tsai, Jeng-Shien Hsieh, En-Hsiang Yeh, Chuei-Tang Wang
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Publication number: 20240152671Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.Type: ApplicationFiled: November 3, 2023Publication date: May 9, 2024Applicant: MEDIATEK INC.Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
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Patent number: 11979156Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.Type: GrantFiled: March 21, 2023Date of Patent: May 7, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
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Publication number: 20240142732Abstract: A method includes forming a first waveguide over a substrate; forming a first layer of low-dimensional material on the first waveguide; forming a first layer of dielectric material over the first layer of low-dimensional material; forming a second layer of low dimensional material on the first layer of dielectric material; and forming a first conductive contact that electrically contacts the first layer of low-dimensional material and a second conductive contact that electrically contacts the second layer of low-dimensional material.Type: ApplicationFiled: January 6, 2023Publication date: May 2, 2024Inventors: Chih-Hsin Lu, Chin-Her Chien, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu
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Publication number: 20240113258Abstract: A light-emitting diode (LED) includes a semiconductor structure, a transparent conducting layer, a first electrode, and a second electrode. The semiconductor structure has a lower surface and an upper surface, and includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked in a laminating direction from the lower surface to the upper surface. The transparent conducting layer is located on the second semiconductor layer. The first electrode is located on the first semiconductor layer. The second electrode is located on the transparent conducting layer. When viewing the semiconductor structure and the transparent conducting layer from above the LED. The semiconductor structure has a shortest side with a length of X ?m.Type: ApplicationFiled: September 27, 2023Publication date: April 4, 2024Applicant: Quanzhou San'an Semiconductor Technology Co., Ltd.Inventors: Liming ZHANG, Renlong YANG, Heying TANG, Quanyang MA, Xingrong CHEN, Chung-Ying CHANG
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Publication number: 20240105682Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang, Yih Wang
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Publication number: 20240088033Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.Type: ApplicationFiled: March 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Kai Chan, Chung-Hao Tsai, Chuei-Tang WANG, Wei-Ting Chen
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Publication number: 20240088078Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.Type: ApplicationFiled: January 4, 2023Publication date: March 14, 2024Inventors: Chung-Hao Tsai, Yih Wang, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 11923315Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
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Publication number: 20230413661Abstract: Described herein are a novel concept of thermally stimulated delayed phosphorescence (TSDP) to harvest light emission from the higher energy triplet excited state via the up-conversion from the lowest-energy triplet excited state by efficient spin-allowed reverse internal conversion as well as the development of TSDP emitters, as exemplified by a novel class of gold(III) compounds with TSDP properties and methods of making and using said compounds. The gold(III) compound includes a triazine-containing cyclometalating tridentate ligand and one auxiliary ligand, both coordinated to a gold(III) metal center. The gold(III) compounds disclosed herein can be used as light-emitting material for fabrication of OLEDs.Type: ApplicationFiled: August 17, 2023Publication date: December 21, 2023Inventors: Vivian Wing-Wah YAM, Man-Chung TANG, Ming-Yi LEUNG, Shiu-Lun LAI, Mei-Yee CHAN
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Patent number: 11770970Abstract: A series of thermally stable and highly luminescent cyclometalated tetradentate ligand-containing gold(III) compounds was designed and synthesized. The cyclometalated tetradentate ligand-containing gold(III) compounds can be used as light-emitting material for fabrication of light-emitting devices. The cyclometalated tetradentate ligand-containing gold(III) compounds can be deposited as a layer or a component of a layer using a solution-processing technique or a vacuum deposition process. The cyclometalated tetradentate ligand-containing gold(III) compounds are robust and can provide electroluminescence with high efficiency and brightness. More importantly, the vacuum-deposited OLEDs demonstrate long operational stabilities with half-lifetime of over 29,700 hours at 100 cd m?2.Type: GrantFiled: November 10, 2022Date of Patent: September 26, 2023Assignee: THE UNIVERSITY OF HONG KONGInventors: Vivian Wing-Wah Yam, Man-Chung Tang, Lok-Kwan Li, Mei-Yee Chan
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Publication number: 20230209709Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, an active element, a driving circuit element, a first connection circuit, a second connection circuit and a conductive connector. The substrate has a first surface and a second surface opposite to the first surface. The active element is disposed on the first surface. The driving circuit element is disposed on the second surface and is overlapped with the active element. The first connection circuit is disposed on the first surface and is connected to the active element. The second connection circuit is disposed on the second surface and is connected to the driving circuit element. The conductive connector penetrates through the substrate and two ends of the conductive connector are electrically connected to the first connection circuit and the second connection circuit, respectively.Type: ApplicationFiled: November 2, 2022Publication date: June 29, 2023Applicant: E Ink Holdings Inc.Inventors: Yi Jiun Wu, Wen-Chung Tang, Yung-Sheng Chang, Cheng-Hao Lee, Yu-Lin Hsu, Kuo-Hsing Cheng
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Publication number: 20230112122Abstract: A series of thermally stable and highly luminescent cyclometalated tetradentate ligand-containing gold(III) compounds was designed and synthesized. The cyclometalated tetradentate ligand-containing gold(III) compounds can be used as light-emitting material for fabrication of light-emitting devices. The cyclometalated tetradentate ligand-containing gold(III) compounds can be deposited as a layer or a component of a layer using a solution-processing technique or a vacuum deposition process. The cyclometalated tetradentate ligand-containing gold(III) compounds are robust and can provide electroluminescence with high efficiency and brightness. More importantly, the vacuum-deposited OLEDs demonstrate long operational stabilities with half-lifetime of over 29,700 hours at 100 cd m?2.Type: ApplicationFiled: November 10, 2022Publication date: April 13, 2023Inventors: Vivian Wing-Wah YAM, Man-Chung TANG, Lok-Kwan LI, Mei-Yee CHAN
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Patent number: 11532795Abstract: A series of thermally stable and highly luminescent cyclometalated tetradentate ligand-containing gold(III) compounds was designed and synthesized. The cyclometalated tetradentate ligand-containing gold(III) compounds can be used as light-emitting material for fabrication of light-emitting devices. The cyclometalated tetradentate ligand-containing gold(III) compounds can be deposited as a layer or a component of a layer using a solution-processing technique or a vacuum deposition process. The cyclometalated tetradentate ligand-containing gold(III) compounds are robust and can provide electroluminescence with high efficiency and brightness. More importantly, the vacuum-deposited OLEDs demonstrate long operational stabilities with half-lifetime of over 29,700 hours at 100 cd m?2.Type: GrantFiled: December 20, 2019Date of Patent: December 20, 2022Assignee: THE UNIVERSITY OF HONG KONGInventors: Vivian Wing-Wah Yam, Man-Chung Tang, Lok-Kwan Li, Mei-Yee Chan
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Patent number: 11362287Abstract: A novel class of gold(III) compounds containing cyclometalated tridentate ligand and one aryl auxiliary ligand, both coordinated to a gold(III) metal center. (a) X is nitrogen or carbon; (b) Y and Z are independently nitrogen or carbon; (c) A is cyclic structure (derivative) of pyridine, quinoline, isoquinoline or phenyl group; (d) B and C are independently cyclic structures (derivatives) of pyridine, quinoline, isoquinoline or phenyl groups; (e) B and C can be identical or non-identical, with the proviso that both B and C are not 4-tert-butylbenzene; (f) R? is a substituted carbon, nitrogen, oxygen or sulfur donor ligand attached to the gold atom; (g) n is zero, a positive integer or a negative integer. wherein R? is selected from, but not limited to, aryl, substituted aryl, heteroaryl, substituted heteroaryl, heterocyclic aryl and substituted heterocyclic aryl, alkoxy, aryloxy, amide, thiolate, sulfonate, phosphide, fluoride, chloride, bromide, iodide, cyanate, thiocyanate or cyanide.Type: GrantFiled: October 3, 2017Date of Patent: June 14, 2022Assignee: THE UNIVERSITY OF HONG KONGInventors: Vivian Wing-Wah Yam, Man Chung Tang, Mei Yee Chan, Chin Ho Lee, Lok Kwan Li
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Patent number: 11274246Abstract: Described herein are gold (III) compounds according to formula (I) for use as emitters in organic light-emitting devices (OLEDs) and methods of making and using said compounds. The gold (III) compound includes a group 15 element containing tridentate ligand and one aryl auxiliary ligand that are both coordinated to the gold (III) metal center to form a series of thermally stable and highly luminescent gold (III) complexes. The gold (III) compounds disclosed herein can be used as light-emitting material for fabrication of OLEDs. The gold (III) compounds can be deposited as a layer or a component of a layer using a solution processing technique or a vacuum deposition process. The gold (III) compounds are robust and can provide electroluminescence with high efficiency and brightness.Type: GrantFiled: September 6, 2018Date of Patent: March 15, 2022Assignee: THE UNIVERSITY OF HONG KONGInventors: Vivian Wing-Wah Yam, Chin-Ho Lee, Man-Chung Tang, Mei-Yee Chan
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Patent number: 11058178Abstract: A moisture-permeable waterproof shoe includes an upper defining an interior space, an inner sleeve inserted into the interior space and having a sleeve body made from a cut piece, and a sole fixed to a bottom portion of the upper. The cut piece includes an upright velvet layer having a plurality of pile yarns woven between a lining layer and an outer fabric layer of the cut piece, and has a main body with a front convex portion, and two wing portions each including a wing lateral edge connected to the wing lateral edge of the other wing portion, a front curved edge connected to a periphery of the front convex portion, and a rear mating edge connected to the rear mating edge of the other wing portion.Type: GrantFiled: August 6, 2019Date of Patent: July 13, 2021Assignee: SHUANG BANG INDUSTRIAL CORP.Inventor: Chung-Tang Chang
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Patent number: 10966487Abstract: A method of making a knitted shoe includes the steps of: (A) preparing a tube main body having opposite first and second openings; (B) closing the first opening to form a front joined part; (C) cutting an oval shaped opening in the tube main body and closing the same to form a side joined part proximate to the front joined part; (D) preparing and sleeving a three-dimensional rigid foam sleeve on a shoe last; (E) adhering the tube main body to an outer surface of the foam sleeve so as to form a tubular knitted upper; (F) placing the shoe last in an oven for heating; (G) removing the shoe last from the oven; (H) adhering a sole to a bottom side of the tubular knitted upper; and (I) removing the shoe last from the tubular knitted upper.Type: GrantFiled: October 26, 2017Date of Patent: April 6, 2021Assignee: SHUANG BANG INDUSTRIAL CORP.Inventor: Chung-Tang Chang
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Patent number: 10951565Abstract: A method for sending a plurality of alternate contact information associated with an online communication system. The method may include receiving an electronic message associated with the online communication system, wherein the electronic message is addressed to a recipient from a sender. The method may also include identifying a recipient inbox using a plurality of directory information associated with the received electronic message. The method may further include determining the identified recipient inbox satisfies at least one of a plurality of alternate contact criteria. The method may also include transmitting a plurality of alternate recipient contact information within a simple message transfer protocol (SMTP) response to the sender based on the plurality of determined alternate contact criteria being satisfied.Type: GrantFiled: October 17, 2019Date of Patent: March 16, 2021Assignee: International Business Machines CorporationInventors: Wai Man Lee, Hon Chung Tang, Ka Chun Wong, Wing Kong Yip