Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A semiconductor package with a reinforced substrate and a fabrication method of the substrate are provided. The substrate is formed of a metal core layer with relatively high rigidity, and an insulating layer is coated on at least a surface of the core layer. At least a ground via is formed through the insulating layer, allowing a chip mounted on the substrate to be electrically connected and grounded to the substrate by the ground via. The reinforced substrate provides the semiconductor package with sufficient mechanical strength, and can be reduced in thickness in favor of package profile miniaturization. Moreover, the substrate made of the metal core layer and insulating layer has a relatively small dielectric constant to facilitate electron transmission velocity, thereby improving electrical quality of the semiconductor package. Furthermore, the metal core layer is made of a thermally-conductive metallic material, and enhances heat dissipating efficiency of the semiconductor package.

Abstract: A circuit board for a flip-chip semiconductor package and a fabrication method of the circuit board are provided. A core layer is coated with a resin material on a surface thereof where a plurality of bond pads are formed. Laser-etching technology is adopted to form a plurality of openings through the resin material corresponding in position to the bond pads, whereby the bond pads are exposed via the openings to be bonded with solder balls or bumps, so as to allow the circuit board to be electrically connected to an external device or a chip via the solder balls or bumps. This circuit board is beneficial to allow precise exposure of the bond pads in position, which can improve quality and yield of the circuit board and make the circuit board suitably applied to high-level products with fine-pitch arrangement of conductive elements for electrical connection purposes.

Abstract: A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.

Abstract: A strengthened bonding mechanism for a semiconductor package is proposed. An aluminum pad formed on a chip is formed with a UBM (under bump metallurgy) structure, on which a tin layer is applied. Moreover, a copper pad formed on a substrate or printed circuit board is formed with a tin layer thereon. Thereby, a solder ball or bump is adapted to be bonded to the tin layer for electrical connection purpose. With provision of the tin layer, the solder ball or bump would be strongly bonded to the bonding mechanism without being easily subject to breaking or cracking, thereby making reliability of fabricated products firmly assured. As such, bonding mechanisms can be densely arrangement so as to reduce pitch spacing between adjacent solder balls or bumps bonded to the bonding mechanisms, in favor of fine-pitch structural arrangement for facilitating electrical connection efficiency.

Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A circuit board free of photo-sensitive material and a fabrication method thereof are proposed, in which at least a surface of a core layer is formed with conductive traces thereon, and a photo-insensitive material is applied over the surface of the core layer in a manner as to hermetically encapsulate the conductive traces, with terminals of the conductive traces being exposed to outside of the photo-insensitive material, whereby solder balls, solder bumps or bonding wires can be bonded to the exposed terminals of the conductive traces, allowing the circuit board to be electrically connected to an external device or a chip by the solder balls, solder bumps or bonding wires. As the photo-insensitive material, instead of solder mask, is applied over the core layer, drawbacks of using conventional solder mask in prior art can be effectively eliminated for the above-fabricated circuit board.

Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed to outside of the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

Abstract: A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second chip mounted on the first chip, is formed with a peripherally-situated cushion member, whereby bonding wires are adapted to extend from bond pads of the second chip in a direction parallel to the chip, and reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the second chip. By the above structure, the bonding wires would be firmly held in position to be free of contact or short circuit with the second chip, and overall package profile can be significantly miniaturized.

Abstract: A low-profile semiconductor device is disclosed which includes a substrate having a base layer formed with at least a hole and a plurality of conductive traces arranged on the base layer. A semiconductor die is attached to the base layer of the substrate opposite to the conductive traces and electrically connected to the conductive traces by a plurality of first conductive elements passing through the hole of the base layer. A plurality of second conductive elements are arrayedly connected to the terminal of each of the conductive traces for providing externally electrical connection to the semiconductor die. The semiconductor die is encapsulated by a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted. A second encapsulant is formed on the surface of the substrate on which the conductive traces are arranged to completely encapsulate the conductive traces, first conductive elements and the hole.