Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.

Abstract: The present invention discloses a method for detecting and examining traumatic brain injury (TBI) in vitro. The method is according to the principle of expression of Etk/Bmx mRNA which is correspondingly increased when TBI occurs, so that the Etk/Bmx mRNA is defined as a quantification reference indicator specific for neurological injury degree of TBI. Thus, the method can be used to detect the expression of the Etk/Bmx mRNA for examining and evaluating the neurological injury degree of TBI occurred due to an external impact.

Abstract: A wireless detection system of physiological signals is provided for wirelessly transmitting variation values of physiological signals, and includes a wireless detecting notification device and a wireless transceiver display device. The wireless detecting notification device comprises at least one transplantable sensor, a connecting line, a printed circuit board, a wireless communication micro-processor chip, an antenna and a power integration module. The power integration module includes a power management chip, a wireless charging coil and a chargeable battery, for integrating a power supply of the wireless detecting notification device. Further, a wireless detection method of physiological signals is further provided to detect variation values of physiological signals in organs of an organism.

Abstract: A capsule endoscope is disclosed. The capsule endoscope includes a shell, a plurality of image capturing units, a positioning unit, and a processing unit. The shell has a containing space. The image capturing units are disposed in the containing space and arranged such that the image capturing units capture images from different angles. The positioning unit is disposed in the containing space for positioning each of the image capturing units. The processing units is disposed in the containing space for acquiring angles of capturing images with the image capturing units according to positioning results of the image capturing units with the positioning unit.

Abstract: The present invention discloses a method for detecting and examining traumatic brain injury (TBI) in vitro. The method is according to the principle of expression of Etk/Bmx protein which is correspondingly increased when TBI occurs, so that the Etk/Bmx protein is defined as a quantification reference indicator specific for neurological injury degree of TBI. Thus, the method can be used to detect the expression of the Etk/Bmx protein for examining and evaluating the neurological injury degree of TBI occurred due to an external impact.

Abstract: Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract: A method and a motherboard for automatically determining the memory type. By applying the characteristics of different operational voltages for various dynamic random access memory modules, a software program is used to drive a control signal and to automatically adjust the control voltage of the dynamic random access memory. An automatic detection of the types of the dynamic random access memory is obtained. The objectives of protecting the dynamic random access memory and to allow the dynamic random access memory to operate normally can thus be achieved. The invention not only provides the detection mechanism for accessing the dynamic random access memory during the initial activation of the computer system, but also determines the voltages required by the memory module for the computer system to enter various power saving modes.

Abstract: A method for verifying error correction code (ECC) function of a computer system is provided. The method includes of enabling the ECC function and writing first test data into the ECC memory. Further, the ECC module will store verifying data according to the first test data. Second, disable the ECC function and overwrite the first test data with second test data. Finally, enable the ECC function to try to recover the first test data by using the second test data and the verifying data.

Abstract: A method and a motherboard for automatically determining the memory type. By applying the characteristics of different operational voltages for various dynamic random access memory modules, a software program is used to drive a control signal and to automatically adjust the control voltage of the dynamic random access memory. An automatic detection of the types of the dynamic random access memory is obtained. The objectives of protecting the dynamic random access memory and to allow the dynamic random access memory to operate normally can thus be achieved. The invention not only provides the detection mechanism for accessing the dynamic random access memory during the initial activation of the computer system, but also determines the voltages required by the memory module for the computer system to enter various power saving modes.

Abstract: A method for setting timing of a system memory in a computer system. The system memory includes a number of memory modules. Each memory module optionally includes individual serial presence detect (SPD) data which record the characteristics of the memory module. Individual SPD data includes a module operating frequency and a set of timing values for the corresponding memory module. The method includes steps as follows: reading individual SPD data of each memory module successively for finding a system memory operating frequency that is operable for all of the memory modules and determining each set of timing values of each memory module; and initializing the system memory according to the system memory operating frequency and each set of timing values.