Abstract: A light-emitting device includes a semiconductor laminate, a first electrode and a second electrode. The semiconductor laminate has a mesa surface, an upper surface, a connecting surface that connects the upper surface and the mesa surface, and a lower surface opposite to the mesa surface and the upper surface. The semiconductor laminate includes a first semiconductor layer, an active layer, and a second semiconductor layer disposed in such order in a direction from the lower surface to the upper surface. The semiconductor laminate has at least one trench that extends from the mesa surface into the first semiconductor layer. The first electrode is electrically connected to the first semiconductor layer and formed on the mesa surface, and has an extending portion that extends into the trench. The second electrode is electrically connected to the second semiconductor layer and formed on the upper surface.

Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.

Abstract: A wearable device includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a fifth radiation element. The first radiation element has a feeding point, and is coupled to a first grounding point on the ground element. A slot region is surrounded by the first radiation element and the ground element. The second radiation element is coupled to a second grounding point on the ground element. The third radiation element is coupled to the second grounding point. The third radiation element and the second radiation element substantially extend in opposite directions. The fourth radiation element and the fifth radiation element are disposed inside the slot region. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element.

Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.

Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.

Abstract: A light-emitting diode (LED) includes a semiconductor structure, a transparent conducting layer, a first electrode, and a second electrode. The semiconductor structure has a lower surface and an upper surface, and includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked in a laminating direction from the lower surface to the upper surface. The transparent conducting layer is located on the second semiconductor layer. The first electrode is located on the first semiconductor layer. The second electrode is located on the transparent conducting layer. When viewing the semiconductor structure and the transparent conducting layer from above the LED. The semiconductor structure has a shortest side with a length of X ?m.

Abstract: A backlight module and a display device are provided. The backlight module includes a back plate, a light guide plate, a first optical film, an adhesive member, a second optical film and a light source. The light guide plate is disposed in the back plate. The first optical film is disposed above the light guide plate, in which the first optical film has an elongated slot. One portion of the adhesive member is disposed in the elongated slot. The second optical film is disposed above or under the first optical film, and a portion of the second optical film overlaps the elongated slot of the first optical film so as to be adhered on the portion of the adhesive member which is located in the elongated slot. The light source is disposed on the back plate adjacent to a light-incident surface of the light guide plate.

Abstract: A backlight module is provided. The backlight module includes a back plate, at least one first carrying portion, a light guide plate, at least one optical film and a light source. The back plate has a sidewall. The first carrying portion is disposed on the back plate. The light guide plate is disposed on the back plate. The optical film is disposed above the light guide plate, in which the optical film has a notch which is corresponding to the first carrying portion. The light source is disposed on the back plate, in which the light source is disposed adjacent to a light-incident surface of the light guide plate.

Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.

Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.

Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500 .ANG. thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600 .ANG., removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100.degree.-1200.degree. C.