Patents by Inventor Chung-Chiang Min
Chung-Chiang Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240172453Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.Type: ApplicationFiled: January 25, 2024Publication date: May 23, 2024Inventor: Chung-Chiang MIN
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Patent number: 11925032Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.Type: GrantFiled: July 25, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Chung-Chiang Min
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Publication number: 20240023460Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: ApplicationFiled: July 27, 2023Publication date: January 18, 2024Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20230389445Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
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Publication number: 20230380188Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng
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Patent number: 11818962Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: GrantFiled: August 19, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
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Patent number: 11785861Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: GrantFiled: July 15, 2021Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 11785786Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.Type: GrantFiled: May 19, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng
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Patent number: 11665911Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.Type: GrantFiled: July 30, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
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Publication number: 20230100433Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer is disposed on the first electrode. A second electrode overlies the data storage layer. A buffer layer is disposed between the data storage layer and the second electrode.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Chung-Chiang Min, Chang-Chih Huang, Yuan-Tai Tseng, Kuo-Chyuan Tzeng, Yihuei Zhu
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Patent number: 11532785Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.Type: GrantFiled: October 20, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Min, Chang-Chih Huang, Yuan-Tai Tseng, Kuo-Chyuan Tzeng, Yihuei Zhu
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Publication number: 20220367811Abstract: A memory device with hard mask insulator and its manufacturing methods are provided. In some embodiments, the memory device includes a memory cell stack disposed over a substrate. The memory cell stack includes a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is disposed over the top electrode layer, and a first metal hard masking layer disposed over the first insulating layer.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chern-Yow Hsu, Chung-Chiang Min, Shih-Chang Liu
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Publication number: 20220359610Abstract: A memory device including an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a vertical stack containing a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventor: Chung-Chiang MIN
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Patent number: 11495743Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.Type: GrantFiled: May 5, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chern-Yow Hsu, Chung-Chiang Min, Shih-Chang Liu
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Publication number: 20220319920Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
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Publication number: 20220302209Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a first dielectric layer having a first region and a second region. A bottom electrode is at least partially arranged within the first region of the first dielectric layer. A memory element is over the bottom electrode and a top electrode is over the memory element. A second dielectric layer is over at least the first region of the first dielectric layer. The second dielectric layer surrounds the memory element and at least a part of the top electrode. A third dielectric layer is over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer. A conductive interconnect is in the third dielectric layer and the second region of the first dielectric layer. The first dielectric layer has a different non-zero thickness within the first region than within the second region.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
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Patent number: 11437431Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.Type: GrantFiled: January 15, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Chung-Chiang Min
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Publication number: 20220278170Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng
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Patent number: 11380580Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.Type: GrantFiled: August 31, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
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Patent number: 11362265Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: GrantFiled: April 22, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu