Patents by Inventor Chung-Chin TSAI

Chung-Chin TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10320494
    Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 11, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Hwui Chung, Chung-Chin Tsai, Ping-Hsuan Tsu, Chun-Hsien Peng
  • Patent number: 10069578
    Abstract: An integrated circuit (IC) is provided. The IC includes: an RF transmitter configured to generate an RF signal when the IC has entered a test mode; an RF receiver configured to receive the RF signal in the test mode; and a computation unit having a plurality of processing units that are parallelized to perform a test procedure of the IC according to the received RF signal to determine one or more test results.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 4, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chung-Chin Tsai, Chun-Hsien Peng
  • Publication number: 20160204881
    Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 14, 2016
    Inventors: Yuan-Hwui CHUNG, Chung-Chin TSAI, Ping-Hsuan TSU, Chun-Hsien PENG
  • Publication number: 20160197685
    Abstract: An integrated circuit (IC) is provided. The IC includes: an RF transmitter configured to generate an RF signal when the IC has entered a test mode; an RF receiver configured to receive the RF signal in the test mode; and a computation unit having a plurality of processing units that are parallelized to perform a test procedure of the IC according to the received RF signal to determine one or more test results.
    Type: Application
    Filed: March 16, 2016
    Publication date: July 7, 2016
    Inventors: Chung-Chin TSAI, Chun-Hsien PENG
  • Publication number: 20160197684
    Abstract: An integrated circuit (IC) is provided. The IC includes: a controller, a serializer-deserializer (SerDes) device, a transmitter, and a receiver. The controller is configured to obtain a test signal when the IC has entered a test mode. The SerDes device is configured to perform a serialization/deserialization process on the test signal. The transmitter is configured to generate a radio frequency (RF) signal in response to the test signal after the serialization/deserialization process. The RF receiver is configured to receive the RF signal in the test mode. The controller further captures the received RF signal from the receiver for determining a test result.
    Type: Application
    Filed: March 16, 2016
    Publication date: July 7, 2016
    Inventors: Chung-Chin TSAI, Chun-Hsien PENG, Yuan-Hwui CHUNG