Patents by Inventor Chung-Ching Tseng

Chung-Ching Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11144697
    Abstract: A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 12, 2021
    Assignee: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Hsin-Hsiung Yu, Ching-Chong Chuang, Chung-Ching Tseng
  • Patent number: 11126217
    Abstract: An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 21, 2021
    Assignee: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Chung-Ching Tseng, Ching-Chong Chuang
  • Publication number: 20020176567
    Abstract: A method and apparatus for dynamically adjusting receiver sensitivity over an existing phone line home network is disclosed. The method includes what is referred to Continuous Carrier Detect (CCD) adaptation process implemented by a state machine to quickly adapt to the on the fly wire DC offset in a matter of a few milliseconds for achieving optimal receiver sensitivity. According to one embodiment, a noise threshold level is dynamically generated for detecting noises in incoming data stream from the existing phone line home network.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 28, 2002
    Inventors: Cui Chen, Chung-Ching Tseng