Patents by Inventor Chung-Fu Chu

Chung-Fu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 8129513
    Abstract: This invention provides a plant senescence-inducible promoter and its relevant recombinant plasmid and transgenic plant.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 6, 2012
    Assignee: National Taiwan University
    Inventors: Shih-Tong Jeng, Pu-Huan Liu, Chung-Fu Chu
  • Publication number: 20090241231
    Abstract: This invention provides a plant senescence-inducible promoter and its relevant recombinant plasmid and transgenic plant.
    Type: Application
    Filed: September 22, 2008
    Publication date: September 24, 2009
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Tong Jeng, Pu-Huan Liu, Chung-Fu Chu
  • Patent number: 6153530
    Abstract: Disclosed herein is a post-etch treatment for plasma etched metal-comprising features in semiconductor devices. The post-etch treatment significantly reduces or eliminates surface corrosion of the etched metal-comprising feature. It is particularly important to prevent the formation of moisture on the surface of the feature surface prior to an affirmative treatment to remove corrosion-causing contaminants from the feature surface. Avoidance of moisture formation is assisted by use of a high vacuum; use of an inert, moisture-free purge gas; and by maintaining the substrate at a sufficiently high temperature to volatilize moisture.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: November 28, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Xiaoye Zhao, Chang-Lin Hsieh, Xian-Can Deng, Wen-Chiang Tu, Chung-Fu Chu, Diana Xiaobing Ma