Patents by Inventor Chung-Fu Lin
Chung-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164111Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: ApplicationFiled: January 23, 2024Publication date: May 16, 2024Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11985906Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.Type: GrantFiled: March 12, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
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Patent number: 11917831Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: August 5, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20240056601Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video.Type: ApplicationFiled: December 17, 2021Publication date: February 15, 2024Inventors: Harikrishna Madadi Reddy, Xianliang Zha, Junqiang Lan, Sujith Srinivasan, Guogang Hua, Chung-Fu Lin
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Patent number: 11665340Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 21, 2021Date of Patent: May 30, 2023Assignee: Meta Platforms, Inc.Inventors: Junqiang Lan, Guogang Hua, Harikrishna Madadi Reddy, Chung-Fu Lin, Xing Cindy Chen, Sujith Srinivasan
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Publication number: 20230140628Abstract: A system that includes a pixel processing stage decoupled from an entropy coding stage is disclosed. The pixel processing results comprise quantized transform coefficients that are divided into component blocks. The component blocks including non-zero data are identified. An optimized version of the pixel processing results for storage in a buffer storage is generated. The optimized version includes an identification of which of the component blocks include non-zero data, and the optimized version includes contents of one or more of the component blocks that include non-zero data, without including contents of one or more of the component blocks that only include zero data. The optimized version of the pixel processing results is provided for storage in the buffer storage. The optimized version of the pixel processing results from the buffer storage is received and processed to generate an unpacked version of the pixel processing results for use in entropy coding.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Inventors: Srikanth Alaparthi, Karunakar Reddy Rachamreddy, Yunqing Chen, Visalakshi Vaduganathan, Chung-Fu Lin, Harikrishna Madadi Reddy
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Patent number: 11558637Abstract: A system comprises a memory storage configured to store at least a portion of a frame of a video and a hardware motion estimation search processing unit configured to perform at least a portion of a motion estimation search for the video for a plurality of different block sizes. The hardware motion estimation search processing unit is configured to perform the motion estimation search using a plurality of source sub-blocks of a first block size to determine a first type of comparison evaluation values for the first block size. A combination of values included in the first type of comparison evaluation values is utilized to determine at least one second type of comparison evaluation values for a second block size, wherein the second block size is larger than the first block size.Type: GrantFiled: December 16, 2019Date of Patent: January 17, 2023Assignee: Meta Platforms, Inc.Inventors: Xianliang Zha, Harikrishna Madadi Reddy, Junqiang Lan, Sujith Srinivasan, Chung-Fu Lin, Guogang Hua
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Publication number: 20220303525Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 21, 2021Publication date: September 22, 2022Inventors: Junqiang Lan, Guogang Hua, Harikrishna Madadi Reddy, Chung-Fu Lin, Xing Cindy Chen, Sujith Srinivasan
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Patent number: 11234017Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video. Each of the hardware motion estimation search processing units is configured to be assigned a different one of the plurality of different reference frames and is configured to compare at least the portion of the source block with a portion of the assigned one of the different reference frames.Type: GrantFiled: December 13, 2019Date of Patent: January 25, 2022Assignee: Meta Platforms, Inc.Inventors: Harikrishna Madadi Reddy, Xianliang Zha, Junqiang Lan, Sujith Srinivasan, Guogang Hua, Chung-Fu Lin
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Publication number: 20100257415Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.Type: ApplicationFiled: April 1, 2009Publication date: October 7, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Chung-Fu Lin, Yeong-Jar Chang
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Patent number: 7716542Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.Type: GrantFiled: November 13, 2007Date of Patent: May 11, 2010Assignee: Faraday Technology Corp.Inventors: Yeong-Jar Chang, Chung-Fu Lin
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Publication number: 20090125763Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.Type: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventors: Yeong-Jar Chang, Chung-Fu Lin
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Publication number: 20090110102Abstract: A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits.Type: ApplicationFiled: December 29, 2008Publication date: April 30, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventors: Ghia-Ming Hong, Chia-Wei Chang, Yan-Hua Peng, Kuang-Chih Liu, Chung-Fu Lin
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Publication number: 20090040086Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.Type: ApplicationFiled: August 7, 2007Publication date: February 12, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventors: Ghia-Ming Hong, Chia-Wei Chang, Yan-Hua Peng, Kuang-Chih Liu, Chung-Fu Lin
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Patent number: 7486210Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.Type: GrantFiled: August 7, 2007Date of Patent: February 3, 2009Assignee: Faraday Technology Corp.Inventors: Ghia-Ming Hong, Chia-Wei Chang, Yan-Hua Peng, Kuang-Chih Liu, Chung-Fu Lin