Patents by Inventor Chung Geun Koh
Chung Geun Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140374827Abstract: A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain.Type: ApplicationFiled: April 23, 2014Publication date: December 25, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Chan SUH, Chung-Geun KOH, Seong-Hoon JEONG, Kwan-Heum LEE, Hwa-Sung RHEE, Gyeom KIM
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Patent number: 8883651Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.Type: GrantFiled: July 31, 2012Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
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Patent number: 8772095Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.Type: GrantFiled: June 13, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Hoon Kim, Sang-Su Kim, Chung-Geun Koh, Sun-Ghil Lee, Jin-Yeong Joe
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Patent number: 8633078Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.Type: GrantFiled: September 22, 2011Date of Patent: January 21, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan-Yong Lim, Chung-Geun Koh, Sang-Bom Kang, Ui-Hui Kwon, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim
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Publication number: 20130115742Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.Type: ApplicationFiled: June 13, 2012Publication date: May 9, 2013Inventors: Seok-Hoon KIM, Sang-Su KIM, Chung-Geun KOH, Sun-Ghil LEE, Jin-Yeong JOE
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Publication number: 20130045589Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.Type: ApplicationFiled: July 31, 2012Publication date: February 21, 2013Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
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Patent number: 8298926Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.Type: GrantFiled: December 27, 2007Date of Patent: October 30, 2012Assignees: Siltron Inc., Hynix Semiconductor Inc.Inventors: Hyung-Kook Park, Jin-Kyun Hong, Kun Kim, Chung-Geun Koh
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Publication number: 20120108023Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.Type: ApplicationFiled: September 22, 2011Publication date: May 3, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwan-Yong Lim, Chung-Geun Koh, Sang-Bom Kang, Ui-Hui Kwon, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim
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Publication number: 20120034749Abstract: A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.Type: ApplicationFiled: August 3, 2011Publication date: February 9, 2012Inventors: Kwan-Yong LIM, Chung-Geun Koh, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim, Tae-Ho Cha
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Patent number: 8101480Abstract: A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.Type: GrantFiled: November 12, 2010Date of Patent: January 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Hoon Kim, Chung-Geun Koh, Kwan-Yong Lim, Hyun-Jung Lee, Tae-Ouk Kwon, Sang-Bom Kang
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Patent number: 7732352Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.Type: GrantFiled: June 20, 2007Date of Patent: June 8, 2010Assignees: Hynix Semiconductor Inc., Siltron Inc.Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi
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Publication number: 20100038755Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.Type: ApplicationFiled: December 27, 2007Publication date: February 18, 2010Applicants: SILTRON INC., HYNIX SEMICONDUCTOR INC.Inventors: Hyung Kook Park, Jin-Kyun Hong, Kun Kim, Chung-Geun Koh
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Patent number: 7242075Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.Type: GrantFiled: October 31, 2003Date of Patent: July 10, 2007Assignees: Hynix Semiconductor Inc., Siltron Inc.Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi