Patents by Inventor Chung Han Lin

Chung Han Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164109
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 16, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Publication number: 20240105849
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Da-Zhi ZHANG, Chun-An LU, Chung-Yu CHIANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Publication number: 20240105521
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Zhi ZHANG, Chung-Pin HUANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Patent number: 11733378
    Abstract: The present disclosure provides a detection system and a detection method. The microphone of the detection system receives the response signal formed according to the shape of the sealed cavity. The conversion unit transfers the response signal in the time domain to the frequency domain signal in the frequency domain. The calculation unit obtains every frequency value corresponding to the frequency gradient being zero of each frequency waveform which is chosen of the response signal. The average unit averages every frequency value corresponding to the frequency gradient being zero of each chosen frequency waveform into the average frequency value and outputs an average frequency value. The determination unit determines whether the average frequency value is located in the corresponding frequency tolerance range, so that the wearing status of the in-ear earphone is confirmed.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: August 22, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chung-Han Lin, Yueh-Hsiang Chen, Kun-Chi Pan
  • Publication number: 20230176211
    Abstract: The present disclosure provides a detection system and a detection method. The microphone of the detection system receives the response signal formed according to the shape of the sealed cavity. The conversion unit transfers the response signal in the time domain to the frequency domain signal in the frequency domain. The calculation unit obtains every frequency value corresponding to the frequency gradient being zero of each frequency waveform which is chosen of the response signal. The average unit averages every frequency value corresponding to the frequency gradient being zero of each chosen frequency waveform into the average frequency value and outputs an average frequency value. The determination unit determines whether the average frequency value is located in the corresponding frequency tolerance range, so that the wearing status of the in-ear earphone is confirmed.
    Type: Application
    Filed: February 11, 2022
    Publication date: June 8, 2023
    Inventors: Chung-Han Lin, Yueh-Hsiang Chen, Kun-Chi Pan
  • Patent number: 11213256
    Abstract: A biological image processing method is provided. The method acquires first time-frequency data from an image data; processing the first time-frequency data into the second time-frequency data using a filter module; and converting the second time-frequency data into a time domain signal. The filter module is obtained by machine learning, and is trained using a first sample time-frequency signal as input and a second sample time-frequency signal as output, wherein the noise of the time domain signal corresponding to the second sample time-frequency signal is less than the noise of the time domain signal corresponding to the first sample time-frequency signal. A biological information detection device is also provided.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: January 4, 2022
    Assignee: FACEHEART INC.
    Inventors: Tsuey-Huey Shiue, Chung-Shine Huang, Kuan-Hung Chen, Po-Wei Huang, Da-Hong He, Chung-Han Lin
  • Patent number: 10969906
    Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 6, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Huang-Chih Chen, Yueh-Hsiang Chen, Kun-Chi Pan, Yu-Cheng Hsu, Chung-Han Lin
  • Publication number: 20210048916
    Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.
    Type: Application
    Filed: November 21, 2019
    Publication date: February 18, 2021
    Inventors: Huang-Chih Chen, Yueh-Hsiang Chen, Kun-Chi Pan, Yu-Cheng Hsu, Chung-Han Lin
  • Patent number: 10854217
    Abstract: A wind noise filtering device includes a mixer, an extraction unit, a decision unit, a wind noise filter and an output module. The mixer receives a source sound and outputs an input audio. The extraction unit is electrically connected to the mixer to receive the input audio, the extraction unit performs feature extraction on the input audio to generate a plurality of feature data. The decision unit is electrically connected to the extraction unit to receive the feature data, the decision unit outputs a decision signal according to the plurality of feature data. The wind noise filter is electrically connected to the decision unit to receive the decision signal and is controlled to be turned on or off by the decision signal. The output module is electrically connected to the wind noise filter and the mixer to output an output audio according to the input audio or the filtered audio.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 1, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventor: Chung-Han Lin
  • Publication number: 20200330042
    Abstract: A biological image processing method is provided. The method acquires first time-frequency data from an image data; processing the first time-frequency data into the second time-frequency data using a filter module; and converting the second time-frequency data into a time domain signal. The filter module is obtained by machine learning, and is trained using a first sample time-frequency signal as input and a second sample time-frequency signal as output, wherein the noise of the time domain signal corresponding to the second sample time-frequency signal is less than the noise of the time domain signal corresponding to the first sample time-frequency signal. A biological information detection device is also provided.
    Type: Application
    Filed: January 2, 2020
    Publication date: October 22, 2020
    Applicant: FaceHeart Inc.
    Inventors: TSUEY-HUEY SHIUE, CHUNG-SHINE HUANG, KUAN-HUNG CHEN, PO-WEI HUANG, DA-HONG HE, CHUNG-HAN LIN
  • Patent number: 10804083
    Abstract: A cathode assembly for a physical vapor deposition (PVD) system includes a target holder and a thickness detector. The target holder is for holding a target, in which the target has a first major surface and a second major surface. The first major surface and the second major surface are respectively proximal and distal to the target holder. The thickness detector is disposed on the target holder. At least one portion of the first major surface is exposed to the thickness detector for allowing the thickness detector to detect the thickness of the target through the first major surface.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chieh Wang, Cheng-Kuo Wang, Chung-Han Lin
  • Patent number: 9460957
    Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing Long Lee, Yi-Chieh Wang, Chung-Han Lin, Kuang-Jung Peng, Yun Chang, Shou-Wen Kuo
  • Publication number: 20160013032
    Abstract: A cathode assembly for a physical vapor deposition (PVD) system includes a target holder and a thickness detector. The target holder is for holding a target, in which the target has a first major surface and a second major surface. The first major surface and the second major surface are respectively proximal and distal to the target holder. The thickness detector is disposed on the target holder. At least one portion of the first major surface is exposed to the thickness detector for allowing the thickness detector to detect the thickness of the target through the first major surface.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 14, 2016
    Inventors: Yi-Chieh WANG, Cheng-Kuo WANG, Chung-Han LIN
  • Publication number: 20140264720
    Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing Long Lee, Yi-Chieh Wang, Chung-Han Lin, Kuang-Jung Peng, Yun Chang, Shou-Wen Kuo
  • Patent number: 7363436
    Abstract: A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: April 22, 2008
    Assignee: Integrated Device Technology, Inc.
    Inventors: Tzong-Kwang Henry Yeh, Bill Beane, Chung Han Lin, Wei-Ling Chang