Abstract: A memory cell with a recessed bottom electrode and methods of forming the memory cell are described. A bottom electrode can be deposited on a layer of a structure. A first insulator and a second insulator can be deposited on top of the bottom electrode. The first insulator and the second insulator can be spaced apart from one another to form an opening on top of the bottom electrode. A recess can be etched in the bottom electrode. The recess can be etched in a portion of the bottom electrode that is underneath the opening. The recess and the opening can form a pore. Phase change material can be deposited in the pore to form a memory cell.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element and receives first and second pulse signals. Post-neuron circuit includes input, output and integration terminals. Integration terminal is charged to membrane potential according to first pulse signal. Post-neuron circuit further includes first and second control circuits, and first and second delay circuits. First control circuit generates firing signal at output terminal based on membrane potential. Second control circuit generates first control signal based on firing signal. First delay circuit delays firing signal to generate second control signal. Second delay circuit delays second control signal to generate third control signal.

Abstract: The present invention discloses a method for manufacturing a phase change memory and a phase change memory. The method comprises: forming a first wafer having a semiconductor-on-insulator structure; forming a memory material layer on the semiconductor-on-insulator structure; and forming a first metal material layer on the memory material layer to form a first semiconductor element.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element, first switch having at least three terminals, and second switch. Phase change element includes first and second terminals. First switch includes first, second and control terminals. Second switch includes first, second and control terminals. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch, and is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. First switch is coupled to phase change element, and is configured to receive first pulse signal. Second switch is coupled to phase change element. Input terminal of post-neuron circuit is coupled to switch circuit, and input terminal is coupled to phase change element. Input terminal charges capacitor through switch circuit in response to first pulse signal. Post-neuron circuit is configured to generate firing signal based on voltage level at input terminal and threshold voltage, and is further configured to generate first control signal and second control signal based on firing signal. Post-neuron circuit turns off switch circuit according to first control signal. Second control signal is configured to cooperate with second pulse signal to control second switch so as to control a state of phase change element.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. Phase change element includes first terminal and second terminal. First switch includes first terminal and second terminal. Second switch includes first terminal, second terminal, and control terminal. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch. Second switch is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer, a lower electrode layer over the conductive layer, an upper electrode layer, a phase change material between the lower and upper electrode layers, and a selector material between the conductive layer and the lower electrode layer; etching the upper electrode layer to form an upper electrode wire; etching the phase change material according to the upper electrode wire to form a phase change material layer and expose a portion of the lower electrode layer, wherein the phase change material layer has an exposed side surface; after etching the phase change material, performing a nitridizing treatment on the side surface of the phase change material layer to form a nitridized phase change material layer covering the same; and etching the lower electrode layer, the selector material and the conductive layer.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. First switch is coupled to phase change element, and is configured to receive first pulse signal. Second switch is coupled to phase change element. Input terminal of post-neuron circuit is coupled to switch circuit, and input terminal is coupled to phase change element. Input terminal charges capacitor through switch circuit in response to first pulse signal. Post-neuron circuit is configured to generate firing signal based on voltage level at input terminal and threshold voltage, and is further configured to generate first control signal and second control signal based on firing signal. Post-neuron circuit turns off switch circuit according to first control signal. Second control signal is configured to cooperate with second pulse signal to control second switch so as to control a state of phase change element.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element, first switch having at least three terminals, and second switch. Phase change element includes first and second terminals. First switch includes first, second and control terminals. Second switch includes first, second and control terminals. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch, and is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: Artificial neuromorphic circuit includes synapse circuit and post-neuron circuit. Synapse circuit includes phase change element, first switch, and second switch. Phase change element includes first terminal and second terminal. First switch includes first terminal and second terminal. Second switch includes first terminal, second terminal, and control terminal. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch. Second switch is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch.

Abstract: Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element and receives first and second pulse signals. Post-neuron circuit includes input, output and integration terminals. Integration terminal is charged to membrane potential according to first pulse signal. Post-neuron circuit further includes first and second control circuits, and first and second delay circuits. First control circuit generates firing signal at output terminal based on membrane potential. Second control circuit generates first control signal based on firing signal. First delay circuit delays firing signal to generate second control signal. Second delay circuit delays second control signal to generate third control signal.

Abstract: A diode structure includes a substrate, a pillar stack disposed on the substrate, and a first barrier layer. The pillar stack includes a first semiconductor layer, a silicon layer, and a second semiconductor layer, in which the first and second semiconductor layers respectively have different dopants such that a conductivity of the first semiconductor layer is different from a conductivity of the second semiconductor layer. The first barrier layer is disposed between the first semiconductor layer and the silicon layer, in which the first barrier layer is configured to prevent the dopants in the first semiconductor layer from diffusing into the silicon layer.

Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer, a lower electrode layer over the conductive layer, an upper electrode layer, a phase change material between the lower and upper electrode layers, and a selector material between the conductive layer and the lower electrode layer; etching the upper electrode layer to form an upper electrode wire; etching the phase change material according to the upper electrode wire to form a phase change material layer and expose a portion of the lower electrode layer, wherein the phase change material layer has an exposed side surface; after etching the phase change material, performing a nitridizing treatment on the side surface of the phase change material layer to form a nitridized phase change material layer covering the same; and etching the lower electrode layer, the selector material and the conductive layer.

Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.