Patents by Inventor Chung-Hsiang Wang

Chung-Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240304705
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 12087690
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20240280872
    Abstract: The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate and overlapped with the active layer; and a conductive pattern disposed above the substrate. The conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line and overlapped with the active layer.
    Type: Application
    Filed: April 30, 2024
    Publication date: August 22, 2024
    Inventors: Chung-Wen YEN, Yu-Tsung LIU, Chao-Hsiang WANG, Te-Yu LEE
  • Publication number: 20240274715
    Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.
    Type: Application
    Filed: March 21, 2023
    Publication date: August 15, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Hsiang Wang, Yi-Fan Li, Chung-Ting Huang, Chi-Hsuan Tang, Chun-Jen Chen, Ti-Bin Chen, Chih-Chiang Wu
  • Patent number: 10067320
    Abstract: A lens module includes a lens set and a prism. The lens set has a first light emitting surface and a first engaging structure, wherein the first engaging structure is formed on the first light emitting surface. The prism is disposed adjacent to the lens set. The prism has a light incident surface and a second engaging structure, wherein the second engaging structure is formed on the light incident surface. The lens set and the prism are assembled with each other by engaging the first engaging structure with the second engaging structure.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: September 4, 2018
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yin-Dong Lu, Han-Ching Lin, Yu-Feng Yen, Chung-Hsiang Wang
  • Publication number: 20170131529
    Abstract: A lens module includes a lens set and a prism. The lens set has a first light emitting surface and a first engaging structure, wherein the first engaging structure is formed on the first light emitting surface. The prism is disposed adjacent to the lens set. The prism has a light incident surface and a second engaging structure, wherein the second engaging structure is formed on the light incident surface. The lens set and the prism are assembled with each other by engaging the first engaging structure with the second engaging structure.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Yin-Dong Lu, Han-Ching Lin, Yu-Feng Yen, Chung-Hsiang Wang
  • Publication number: 20130256540
    Abstract: The present invention provides a readout device of an accelerator beam monitoring detector, comprising: a transimpedance amplifier receiving a charge signal from a particle detector and converting the charge signal into an analog voltage signal; and a data acquisition system comprising an analog-to-digital converter (ADC) to covert the analog voltage signal into digital data.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 3, 2013
    Applicants: Academia Sinica, National United University, National Central University
    Inventors: PING-KUN TENG, AUGUSTINE EI-FANG CHEN, MING-LEE CHU, CHIH-HSUN LIN, CHUNG-HSIANG WANG
  • Patent number: 8250471
    Abstract: An electronic device and a method for controlling an user interface thereof are provided. The method includes detecting an orientation of the electronic device, determining a arrangement of the user interface according to the detected orientation, displaying a shortcut key area and a status area on the user interface, and adjusting the user interface according to the operational signals from a touch panel of the electronic device.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: August 21, 2012
    Assignees: Shenzhen Futaihong Precision Industry Co., Ltd., FIH (Hong Kong) Limited
    Inventors: Chung-Hsiang Wang, Yu-Sheng Hou, Jian-Cheng Lin, El-Hinn Elizabeth, Pei-Hsi Cheng, Zhi-Fang Chen, Bor-Chuan Lin, Jiing-Renn Yu, Tzu-Cheng Yu
  • Publication number: 20100287469
    Abstract: An electronic device and a method for controlling an user interface thereof are provided. The method includes detecting an orientation of the electronic device, determining a arrangement of the user interface according to the detected orientation, displaying a shortcut key area and a status area on the user interface, and adjusting the user interface according to the operational signals from a touch panel of the electronic device.
    Type: Application
    Filed: November 11, 2009
    Publication date: November 11, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: CHUNG-HSIANG WANG, YU-SHENG HOU, JIAN-CHENG LIN, EL-HINN ELIZABETH, PEI-HSI CHENG, ZHI-FANG CHEN, BOR-CHUAN LIN, JIING-RENN YU, TZU-CHENG YU
  • Patent number: 7795131
    Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: September 14, 2010
    Assignee: Touch Micro-System Technology Inc.
    Inventors: Kuan-Jui Huang, Jie-Mei Huang, Chung-Hsiang Wang
  • Publication number: 20080146021
    Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.
    Type: Application
    Filed: March 12, 2007
    Publication date: June 19, 2008
    Inventors: Kuan-Jui Huang, Jie-Mei Huang, Chung-Hsiang Wang
  • Publication number: 20030133630
    Abstract: A packaging device with a fake-proof adhesive tape is proposed, including a body; a cover integrally formed with the body, for sealing an open end of the body; a fake-proof adhesive tape containing a thin sheet of substrate, and attached to the cover for adhering the cover to the body; a first adhesive layer applied over a first surface of the substrate, for attaching the fake-proof adhesive tape onto the cover; a fake-proof mark layer printed on a second surface of the substrate, and being adherent with the substrate; a colored layer for covering the mark layer and the second surface of the substrate; a transparent or semi-transparent viscous film applied over the colored layer; and a second adhesive layer formed on the viscous film, for adhering the fake-proof adhesive tape to the body.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 17, 2003
    Inventor: Chung-Hsiang Wang