Patents by Inventor Chung-Hsing Liao

Chung-Hsing Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230025696
    Abstract: An electromagnetic wave transmission board proofed against internal signal leakage includes an inner plate, a first outer plate, a second outer plate, a first plate bump, a first conductive bump, a second plate bump, and a second conductive bump. The inner plate defines a first through hole with a plated metal layer on the hole wall. The first and second plated bumps are disposed between the first outer and inner plates. The second plate bump and the second conductive bump are disposed between the second outer plate and the inner plate. The plate metal layer, the first plate bump, the first conductive bump, the first outer plate, the second outer plate, the second conductive bump, and the second plated bump jointly form an air-filled chamber. A method for manufacturing the electromagnetic wave transmission board is also provided.
    Type: Application
    Filed: July 30, 2021
    Publication date: January 26, 2023
    Inventor: CHUNG-HSING LIAO
  • Patent number: 11129283
    Abstract: An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: September 21, 2021
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventors: Chien-Cheng Lee, Chung-Hsing Liao
  • Publication number: 20200170124
    Abstract: An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.
    Type: Application
    Filed: March 18, 2019
    Publication date: May 28, 2020
    Inventors: CHIEN-CHENG LEE, CHUNG-HSING LIAO
  • Patent number: 9860990
    Abstract: A circuit board structure with chips embedded therein includes a multi-layer board and a power module embedded in the multi-layer board. The power module includes an insulating material, a power unit covered by the insulating material, and a circuit layer disposed on the insulating material. The power unit includes an electrically and thermally conductive carrier and a plurality of power chips. The electrically and thermally conductive carrier includes a transmitting portion and a carrying portion perpendicularly connected to the transmitting portion. Each power chip has a first electrode layer and an opposite second electrode layer. The first electrode layers are fixed on and electrically connected to the carrying portion in parallel, and the power chips are disposed at one side of the transmitting portion. The circuit layer is electrically connected to the electrically and thermally conductive carrier and the second electrode layers.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 2, 2018
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventors: Chien-Cheng Lee, Wen-Feng Cheng, Chung-Hsing Liao
  • Patent number: 9271387
    Abstract: A circuit board structure manufacturing method includes the following steps. A circuit substrate is provided including an insulating layer, a first metal layer, and a second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer has a first cavity. The insulating layer has a second cavity and a provisional region. A width of the first cavity is larger than a width of the second cavity. The provisional region is defined between a sidewall of the first metal layer defining the first cavity and another sidewall of the first metal layer defining the second cavity. A first masking layer is formed to cover the first metal layer and provisional region. The second cavity is exposed from the first masking layer. A heat-dissipating metal member is formed in the second cavity. Furthermore, the first masking layer is removed.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Boardtek Electronics Corporation
    Inventors: Chien-Cheng Lee, Chung-Hsing Liao
  • Publication number: 20150052742
    Abstract: A circuit board structure manufacturing method includes the following steps. A circuit substrate is provided including an insulating layer, a first metal layer, and a second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer has a first cavity. The insulating layer has a second cavity and a provisional region. A width of the first cavity is larger than a width of the second cavity. The provisional region is defined between a sidewall of the first metal layer defining the first cavity and another sidewall of the first metal layer defining the second cavity. A first masking layer is formed to cover the first metal layer and provisional region. The second cavity is exposed from the first masking layer. A heat-dissipating metal member is formed in the second cavity. Furthermore, the first masking layer is removed.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: BOARDTEK ELECTRONICS CORPORATION
    Inventors: CHIEN-CHENG LEE, Chung-Hsing Liao