Patents by Inventor Chung-Hsiung Chang

Chung-Hsiung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961892
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 11929417
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20090195187
    Abstract: A LED driving topology includes a LED array and a current source connected in series between two power inputs receiving a positive voltage and a negative voltage respectively. This topology increases the voltage difference across the LED array and hence has the capability of lighting up more serially connected LEDs, without requiring an additional boost circuit or a high voltage. In addition, the circuit of the current source can be made by a low-voltage manufacturing process.
    Type: Application
    Filed: March 5, 2009
    Publication date: August 6, 2009
    Inventors: Chung-Tsung Chen, Chung-Hsiung Chang, Tsan-Huei Wu, Shih-Hui Chen
  • Patent number: 5236276
    Abstract: A method for applying an asphalt layer on a construction surface comprises the steps of placing an asphalt lattice having an admixture of fibrous and particulate matter onto the construction surface, and heating the lattice with a flame so as to melt the asphalt mixture causing it to flow over the surface and fill any depressions and cracks thereon. The asphalt layer thus formed is in intimate contact with the surface and can be used as waterproofing or as a primer layer for further applications of asphalt.
    Type: Grant
    Filed: August 19, 1991
    Date of Patent: August 17, 1993
    Inventors: Chung-Hsiung Chang, Po-Hsing Chang