Patents by Inventor Chung-Hsu Chen

Chung-Hsu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 6452464
    Abstract: An acoustic charge transport device is formed by a process which introduces a process dependent variation in charge carrier density within the device. The acoustic charge transport device includes a transport channel operable to carry charge carriers in response to a surface acoustic wave. In addition, the acoustic charge transport device further includes a backgate for controlling the charge carrier density within the transport channel.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: September 17, 2002
    Assignee: TRW Inc.
    Inventors: Chung-Hsu Chen, Daniel K. Ko, Edward M. Garber, Scott R. Olson, Dwight Christopher Streit
  • Patent number: 5463275
    Abstract: This invention discloses an emitter for a vacuum microelectronic device. The emitter includes a heterojunction step-doped barrier comprised of a first gallium arsenide region, an aluminum gallium arsenide region adjacent the first gallium arsenide region, and a second gallium arsenide region adjacent the aluminum gallium region and opposite to the first gallium arsenide region. The first gallium arsenide region includes a layer of heavily doped n-type gallium arsenide. The aluminum gallium arsenide region includes an intrinsic layer and a heavily doped p-type layer. The second gallium arsenide region includes a heavily doped p-type layer adjacent the aluminum gallium arsenide region, an intrinsic layer and a heavily doped n-type layer adjacent a vacuum region. In addition, a graded layer between the first gallium arsenide layer region and the aluminum gallium arsenide region is provided.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: October 31, 1995
    Assignee: TRW Inc.
    Inventors: Chung-Hsu Chen, Huan-Chun Yen