Patents by Inventor Chung-Hu Ke
Chung-Hu Ke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9673105Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.Type: GrantFiled: April 22, 2013Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Publication number: 20140094008Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.Type: ApplicationFiled: April 22, 2013Publication date: April 3, 2014Applicant: Taiwan Seminconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 8569837Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.Type: GrantFiled: May 7, 2007Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
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Patent number: 8426298Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.Type: GrantFiled: May 23, 2011Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 8154107Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.Type: GrantFiled: February 7, 2007Date of Patent: April 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hu Ke, Chih-Hsin Ko, Wen-Chin Lee
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Patent number: 8084305Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.Type: GrantFiled: February 25, 2008Date of Patent: December 27, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chung-Hu Ke
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Patent number: 8039284Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.Type: GrantFiled: December 18, 2006Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee
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Patent number: 8030210Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.Type: GrantFiled: March 11, 2010Date of Patent: October 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
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Publication number: 20110223727Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 7985652Abstract: A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.Type: GrantFiled: September 14, 2007Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ke, Ta-Ming Kuan, Chih-Hsin Ko, Wen-Chin Lee
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Patent number: 7875959Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.Type: GrantFiled: August 31, 2005Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ke, Wen-Chin Lee, Chenming Hu
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Patent number: 7803718Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.Type: GrantFiled: October 29, 2008Date of Patent: September 28, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Publication number: 20100167485Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 7745904Abstract: A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.Type: GrantFiled: May 31, 2007Date of Patent: June 29, 2010Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chih-Hsin Ko, Chung-Hu Ke, Chien-Chao Huang
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Patent number: 7737532Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.Type: GrantFiled: September 6, 2005Date of Patent: June 15, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee, Min-Hwa Chi
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Patent number: 7709903Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.Type: GrantFiled: May 25, 2007Date of Patent: May 4, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
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Patent number: 7582934Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.Type: GrantFiled: March 1, 2008Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chung-Hu Ke
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Patent number: 7569896Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.Type: GrantFiled: May 22, 2006Date of Patent: August 4, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Chung-Hu Ke, Hung-Wei Chen, Wen-Chin Lee
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Patent number: 7538398Abstract: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/drain region, and one or more contact hole filling metals disposed over and in contact with the at least one non-silicided conductive layer, wherein a first contact area between the at least one non-silicided conductive layer and the source/drain region is substantially larger than a second contact area between the one or more contact hole filling metals and the at least one non-silicided conductive layer.Type: GrantFiled: June 21, 2007Date of Patent: May 26, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hu Ke, Ching-Ya Wang, Wen-Chin Lee
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Publication number: 20090117695Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.Type: ApplicationFiled: October 29, 2008Publication date: May 7, 2009Inventors: Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee