Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: A method for motion prediction includes receiving spatial information output by a radio-wave sensor, wherein the spatial information includes position and velocity of at least one point; receiving an image captured by a camera; tracking at least one object based on the spatial information and the image to obtain a consolidated tracking result; predicting a motion trajectory of the at least one object based on the consolidated tracking result to obtain a prediction result; and controlling the camera according to the prediction result.

Abstract: The present disclosure provides a system and method for enabling an administrator or a controller to update BIOS setup options on a server system and then automatically update the BIOS setup options on other server systems in a baseboard management controller (BMC) virtual local area network (VLAN). For example, the method may comprise: receiving, at a specific controller of a node, a command to update the BIOS setup option; determining whether the specific controller is a master by checking an internal flag of the specific controller; in an event that the specific controller is neither a master or a slave, broadcasting a master request to the VLAN; determining whether a reply is received within a predetermined time period; in an event that the reply is not received, setting the internal flag of the specific controller as a master; and sending an original equipment manufacturer (OEM) completion response.

Abstract: A system and method for automatic recovery of a firmware image is disclosed. The method can include creating a shadow firmware image in a storage device from a firmware image in non-volatile memory. It is determined whether an abnormal event affecting the firmware image has occurred. The shadow firmware image is recovered from the storage device. The shadow firmware image is copied to the non-volatile memory.

Abstract: A system and method for automatic recovery of a firmware image is disclosed. The method can include creating a shadow firmware image in a storage device from a firmware image in non-volatile memory. It is determined whether an abnormal event affecting the firmware image has occurred. The shadow firmware image is recovered from the storage device. The shadow firmware image is copied to the non-volatile memory.

Abstract: The present disclosure provides a system and method for enabling an administrator or a controller to update BIOS setup options on a server system and then automatically update the BIOS setup options on other server systems in a baseboard management controller (BMC) virtual local area network (VLAN). For example, the method may comprise: receiving, at a specific controller of a node, a command to update the BIOS setup option; determining whether the specific controller is a master by checking an internal flag of the specific controller; in an event that the specific controller is neither a master or a slave, broadcasting a master request to the VLAN; determining whether a reply is received within a predetermined time period; in an event that the reply is not received, setting the internal flag of the specific controller as a master; and sending an original equipment manufacturer (OEM) completion response.

Abstract: A synchronization controller for a multi-sensor camera device includes a detection circuit and a control circuit. The detection circuit detects asynchronization between image outputs generated from the multi-sensor camera device, wherein the image outputs correspond to different viewing angles. The control circuit controls an operation of the multi-sensor camera device in response to the asynchronization detected by the detection circuit. In addition, a synchronization method applied to a multi-sensor camera device includes following steps: detecting asynchronization between image outputs generated from the multi-sensor camera device, wherein the image outputs correspond to different viewing angles; and controlling an operation of the multi-sensor camera device in response to the detected asynchronization.

Abstract: A video frame processing method, which comprises: (a) capturing at least one first video flame via a first camera; (b) capturing at least one second video frame via a second camera; and (c) adjusting one candidate second video frame of the second video frames based on one of the first video frame to generate a target single view video frame.

Abstract: An on-line stereo camera calibration method employed by an electronic device with a stereo camera device includes: retrieving a feature point set, and utilizing a stereo camera calibration circuit on the electronic device to calculate a stereo camera parameter set based on the retrieved feature point set. In addition, an on-line stereo camera calibration device on an electronic device with a stereo camera device includes a stereo camera calibration circuit. The stereo camera calibration circuit includes an input interface and a stereo camera calibration unit. The input interface is used to retrieve a feature point set. The stereo camera calibration unit is used to calculate a stereo camera parameter set based on at least the retrieved feature point set.

Abstract: A video frame processing method, which comprises: (a) capturing at least one first video frame via a first camera; (b) capturing at least one second video frame via a second camera; and (c) adjusting one candidate second video frame of the second video frames based on one of the first video frame to generate a target single view video frame.

Abstract: A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.

Abstract: A video frame processing method, which comprises: (a) capturing at least two video frames via a multi-view camera system comprising a plurality of cameras; (b) recording timestamps for each the video frame; (c) determining a major camera and a first sub camera out of the multi-view camera system, based on the timestamps, wherein the major camera captures a major video sequence comprising at least one major video frame, the first sub camera captures a video sequence of first view comprising at least one video frame of first view; (d) generating a first reference video frame of first view according to one first reference major video frame of the major video frames, which is at a reference timestamp corresponding to the first reference video frame of first view, and according to at least one the video frame of first view surrounding the reference timestamp; and (e) generating a multi-view video sequence comprising a first multi-view video frame, wherein the first multi-view video frame is generated based on the

Abstract: An image generation method includes: determining at least one first image capture setting and at least one second image capture setting; controlling an image capture device to generate a plurality of first successive captured images for a capture trigger event according to the at least one first image capture setting and generate a plurality of second successive captured images for the same capture trigger event according to the at least one second image capture setting. Variation of the at least one first image capture setting is constrained within a first predetermined range during generation of the first successive captured images. Difference between the at least one first image capture setting and the at least one second image capture setting is beyond the first predetermined range. Variation of the at least one second image capture setting is constrained within a second predetermined range during generation of the second successive captured images.

Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.

Abstract: An image generation method includes: determining at least one first image capture setting and at least one second image capture setting; controlling an image capture device to generate a plurality of first successive captured images for a capture trigger event according to the at least one first image capture setting and generate a plurality of second successive captured images for the same capture trigger event according to the at least one second image capture setting. Variation of the at least one first image capture setting is constrained within a first predetermined range during generation of the first successive captured images. Difference between the at least one first image capture setting and the at least one second image capture setting is beyond the first predetermined range. Variation of the at least one second image capture setting is constrained within a second predetermined range during generation of the second successive captured images.

Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Abstract: An on-line stereo camera calibration method employed by an electronic device with a stereo camera device includes: retrieving a feature point set, and utilizing a stereo camera calibration circuit on the electronic device to calculate a stereo camera parameter set based on the retrieved feature point set. In addition, an on-line stereo camera calibration device on an electronic device with a stereo camera device includes a stereo camera calibration circuit. The stereo camera calibration circuit includes an input interface and a stereo camera calibration unit. The input interface is used to retrieve a feature point set. The stereo camera calibration unit is used to calculate a stereo camera parameter set based on at least the retrieved feature point set.