Patents by Inventor Chung-Ju Lee

Chung-Ju Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY
    Publication number: 20220302025
    Abstract: Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • THE NOVEL DOUBLE PATTERNING APPROACH BY DIRECT METAL ETCH
    Publication number: 20220285214
    Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: HSI-WEN TIEN, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20220277995
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • MAGNETIC TUNNEL JUNCTION DEVICES
    Publication number: 20220271217
    Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
  • Method for forming semiconductor device with self-aligned conductive features
    Patent number: 11404367
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee
  • SELF-ALIGNED CAVITY STRUCUTRE
    Publication number: 20220230963
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • Semiconductor structure and method for forming the same
    Patent number: 11393718
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih-Wei Lu, Chung-Ju Lee
  • Method of fabricating semiconductor device with reduced trench distortions
    Patent number: 11387113
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability
    Patent number: 11362030
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Integrated circuit
    Patent number: 11355701
    Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • SELF-ALIGNED VIA STRUCTURES AND METHODS
    Publication number: 20220165661
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Magnetic tunnel junction devices
    Patent number: 11329216
    Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Self-aligned cavity strucutre
    Patent number: 11302641
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
    Publication number: 20220084875
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih Wei LU, Chung-Ju LEE
  • ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
    Publication number: 20220059404
    Abstract: Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Sunil Kumar Singh, Chung-Ju Lee, Tien-I Bao
  • SIMULATED SYSTEM AND METHOD WITH AN INPUT INTERFACE
    Publication number: 20220050527
    Abstract: A simulated system with an input interface includes an image capture device that captures an image of hands of a user; an image generating device that generates a computer-generated image of a keyboard including a plurality of keys; a superimposing device that superimposes the computer-generated image and the captured image; and a tracking device that tracks motion of thumbs of the hands according to a plurality of the superimposed images to determine whether a key stroke is made by the thumb.
    Type: Application
    Filed: August 12, 2020
    Publication date: February 17, 2022
    Inventor: Chung-Ju Lee
  • Self-aligned via structures with barrier layers
    Patent number: 11251118
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Methods Of Etching Metals In Semiconductor Devices
    Publication number: 20220044941
    Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • INTEGRATED CHIP WITH CAVITY STRUCTURE
    Publication number: 20220013403
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • SELF-ALIGNED CAVITY STRUCUTRE
    Publication number: 20210391261
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai