Abstract: Methods, systems, and apparatuses, including electrical circuitry, are described for auto-negotiation. Active cables, active backplanes, and line cards may include one or more instances of electrical circuitry and/or integrated circuits that intercept advertisements of standard auto-negotiation protocol signaling from an initiating device for establishment of communication links with a receiving device. Auto negotiation information in the intercepted signaling may be translated and encoded into signaling in accordance with the capabilities of the receiving device. Active cables and active backplanes may also include one or more connection components between instances of electrical circuitry and/or integrated circuits to provide high-speed transmission of data packets encapsulating the auto-negotiation information in a format that differs from the standard auto-negotiation protocol.

Abstract: Methods, systems, and apparatuses, including electrical circuitry, are described for auto-negotiation. Active cables, active backplanes, and line cards may include one or more instances of electrical circuitry and/or integrated circuits that intercept advertisements of standard auto-negotiation protocol signaling from an initiating device for establishment of communication links with a receiving device. Auto negotiation information in the intercepted signaling may be translated and encoded into signaling in accordance with the capabilities of the receiving device. Active cables and active backplanes may also include one or more connection components between instances of electrical circuitry and/or integrated circuits to provide high-speed transmission of data packets encapsulating the auto-negotiation information in a format that differs from the standard auto-negotiation protocol.

Abstract: Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.

Abstract: A communication system and a method are provided. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code.

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract: Techniques, systems and apparatus are described for implementing an inter-channel ring interface in a communication device. A communication device can include communication channels to carry data at respective first data throughputs. An inter-channel ring interface connects at least some of the communication channels in a ring configuration to form an aggregated group of channels that operates as a single channel at a second data throughput.

Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such (e.g.

Abstract: Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.

Abstract: A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code.

Abstract: Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.).

Abstract: Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block and encoding a data stream including the transcoded block.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract: Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits.

Abstract: Embodiments include a decision feedback equalizer (DFE) that includes a first comparator configured to receive as inputs a soft value and a first threshold, a second comparator configured to receive as inputs the soft value and a second threshold, a selector configured to select an output of either the first comparator or the second comparator as a DFE output based on one or more previous bits output by the selector; an error calculator configured to determine an error for the first comparator and the second comparator, and a threshold adjuster configured to adjust the first threshold and the second threshold, the first threshold and the second threshold each being a non-linear combination of one or more previous outputs of the selector.

Abstract: Techniques, systems and apparatus are described for implementing an inter-channel ring interface in a communication device. A communication device can include communication channels to carry data at respective first data throughputs. An inter-channel ring interface connects at least some of the communication channels in a ring configuration to form an aggregated group of channels that operates as a single channel at a second data throughput.

Abstract: Certain aspects of the invention for seamless port bypass controller operations for storage systems, for example, and may comprise a first port of a port bypass controller that receives an input signal and at least one of a plurality of selectors that selects at least a second port coupled in a chain to the first port. At least one of the selectors may switch at least a portion of the received input signal from the first port to at least the second port without initializing or reconfiguring the second port. A repeater may repeat at least a portion of the received input signal to the second port without initializing or reconfiguring the second port. A retimer may generate a retimed signal corresponding to at least a portion of the received input signal to the second port without initializing or reconfiguring the second port.