Abstract: A biosensor of the invention is a capacitive noncontact sensor with two sensor channels split into a plurality of physically interdigitated symmetrical electrodes and shield sections. Two capacitive plates are electrically connected to the two sensor channels. The capacitive noncontact sensor is sized and packaged to be worn by a person to place the capacitive plates close to the skin of the person and form first and second channel input capacitors with the skin. A signal reconstruction circuit obtains a bio signal from the first and second channel input capacitors through the electrodes by reconstructing differences in the two sensor channels. The circuit includes different parasitic input capacitance in the two channels to create channel-specific outputs that depend on input coupling capacitance.

Abstract: A biosensor of the invention is a capacitive noncontact sensor with two sensor channels split into a plurality of physically interdigitated symmetrical electrodes and shield sections. Two capacitive plates are electrically connected to the two sensor channels. The capacitive noncontact sensor is sized and packaged to be worn by a person to place the capacitive plates close to the skin of the person and form first and second channel input capacitors with the skin. A signal reconstruction circuit obtains a bio signal from the first and second channel input capacitors through the electrodes by reconstructing differences in the two sensor channels. The circuit includes different parasitic input capacitance in the two channels to create channel-specific outputs that depend on input coupling capacitance.

Abstract: Designs and techniques for transmitting electrical signals via transmission lines on integrated circuits without distortion and at the speed of light. In one implementation, one or more leakage resistors are connected between the two conductor wires of a transmission line.

Abstract: Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.

Abstract: This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to the grid coarsening and error smoothing operations to increase the processing speed.

Abstract: Designs and techniques for transmitting electrical signals via transmission lines on integrated circuits without distortion and at the speed of light. In one implementation, one or more leakage resistors are connected between the two conductor wires of a transmission line.

Abstract: The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers of a clock distribution tree. In preferred embodiments of the invention, an H-tree clock distribution scheme is overlayed with a spiral of transmission lines, each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line connects drivers in the H-tree that are at the same level of the H-tree.

Abstract: A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected.

Abstract: Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.

Abstract: Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.

Abstract: The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers of a clock distribution tree. In preferred embodiments of the invention, an H-tree clock distribution scheme is overlayed with a spiral of transmission lines, each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line connects drivers in the H-tree that are at the same level of the H-tree.

Abstract: Techniques for performing circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.

Abstract: This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to the grid coarsening and error smoothing operations to increase the processing speed.

Abstract: A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected.

Abstract: An EDA tool is provided with a placement and routing (P&R) module that optimizes placement and routing of an IC design in an interconnect delay driven manner. The P&R module systematically determines if it can improve (i.e. reduce) interconnect delay of the current critical interconnect routing path by determining if it can improve the interconnect delays of its constituting segments, each interconnecting two pins through a component. For each segment, the P&R module determines if the interconnect delay can be achieved by using different interconnect routing path interconnecting the two pins through the component replaced at a different location, and alternatively, through a logically equivalent component disposed at a different location.

Abstract: An EDA tool is provided with a floorplan generator to automatically generate an optimized floorplan for an IC design having a number of design blocks. The floorplanner generates an initial O-tree representation for the design blocks. The floorplanner then perturbs the O-tree representation to seek an alternate O-tree representation that represents an optimized placement of the design blocks in accordance with a cost function. The floorplanner performs the perturbation systematically for all design blocks, traversing the O-tree representation in a depth-first manner and removing one design block at a time. In one embodiment, for each removed design block, the floorplanner also seeks an appropriate re-insertion point for the removed design block systematically by traversing a reduced version of the O-tree representation augmented with candidate insertion points in a depth-first manner.