Abstract: Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.

Abstract: Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric.

Abstract: A propagation delay in the transmission of a frame from an initiator node to a peer node is determined by initially identifying a frame number and byte offset of a first incoming frame from the peer node at a time when the initiator node outputs a portion of a transmitted frame. The portion of the transmitted frame may be the first byte of a sub-frame within the transmitted frame. At the peer node, the frame number and byte offset of a second frame to be supplied to the initiator node is identified at a later time when the frame portion transmitted by the initiator node is received by the peer node, and such information is transmitted to the initiator node. Thus, since the frames output and received by the initiator node are typically of fixed duration, the frame number and byte offset of the incoming frame represent the time when the initiator node outputs the frame portion (a transmit time).

Abstract: An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.

Abstract: A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.

Abstract: A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit.

Abstract: Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.

Abstract: A system and method for rendering a graphic primitive by linear or perspective interpolation from vertex points. An interpolation engine is employed to interpolate channel values along edges of the primitive to determine values along a scan line containing a selected point. The interpolation engine is then employed to interpolate along the scan line. Processing time may further be reduced by the use of an improved adder/subtractor as a component of the interpolation engine to reduce sequential steps and improve parallelism.

Abstract: A striping algorithm selects a route on which to transmit each next data segment, in dependence upon relative channel loading so far, taking account of multicast. Input modules can keep a channel loading history for each route it has, and can update its history for each route that a data segment follows through the fabric. In an embodiment, the input module transmits each data segment toward an i'th intermediate stage module, where i minimizes q(i,a(G),c)+q(i,b(G),c)+ . . . +q(i,k(G),c), where q(i, j, c) indicates the number of bytes of data sent, during a given prior time period, from the input module to each j'th one of the output modules via each i'th one of the intermediate stage modules, and a(G), b(G), . . . , and k(G) are the output module(s) in the multicast group G to which the data segment is destined.