Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: An electrophoretic display able to operate on a reduced power supply includes a display panel and a driving circuit electrically connected to the display panel. The display panel includes a plurality of first electrophoretic particles and a plurality of second electrophoretic particles. The driving circuit is configured to provide a balance signal to the display panel during a balance period, provide a mixed signal to the display panel during a mixing period, and provide a driving signal to the display panel during a coloring period. The balance period, the mixing period, and the coloring period are sequential in time, and a preset time interval is between each of the periods.

Abstract: An electrophoretic display able to operate on a reduced power supply includes a display panel and a driving circuit electrically connected to the display panel. The display panel includes a plurality of first electrophoretic particles and a plurality of second electrophoretic particles. The driving circuit is configured to provide a balance signal to the display panel during a balance period, provide a mixed signal to the display panel during a mixing period, and provide a driving signal to the display panel during a coloring period. The balance period, the mixing period, and the coloring period are sequential in time, and a preset time interval is between each of the periods.

Abstract: The present invention provides a structure and a method of electrically connecting wiring layers by forming a stacked plug interconnect. The first wiring layer is formed over a dielectric layer and a top barrier layer is formed over the top of the first wire layer. Next, first sidewall spacers preferably composed of titanium nitride and tungsten are formed on the first wire layer sidewalls. An inter metal dielectric layer is formed over the surface. A via is then etched exposing the first wiring layer. The first titanium nitride/tungsten spacers act as an etch stop for the via etch and also increase the contact area of the wiring layers. A tungsten plug with an outer TiN barrier layer is formed filling the via contacting the first wiring layer. On top of the tungsten plug, a second wiring layer is formed also having titanium nitride and tungsten sidewall spacers. The spacers also fill in the recesses in the TiN plug barrier layer and fill in dimples in the top of the tungsten plugs.

Abstract: A polysilicon resistor structure for use within integrated circuits and a method by which the polysilicon resistor structure may be formed. A first insulating layer which is formed from a glasseous material is formed directly upon the surface of a semiconductor substrate. A polysilicon resistor is formed in contact with the first insulating layer. A second insulating layer is formed directly upon the first insulating layer and over the polysilicon resistor. The second insulating layer is formed from a silicon oxide material deposited through a Plasma Enhanced Chemical Vapor Deposition process employing silane as the silicon source material.

Abstract: A process for creating tungsten plugs, to fill high aspect ratio contact holes, has been developed. Narrow seams in the center of a tungsten plug, are protected from the tungsten RIE etch back process, thus avoiding the creation of larger seams or voids. This is accomplished by delaying the tungsten RIE etch back step until formation of an overlying interconnect metallization structure, which will protect the underlying tungsten plug, and seam, during the subsequent tungsten RIE etch back procedure.

Abstract: The present invention provides a structure and a method of electrically connecting wiring layers by forming a stacked plug interconnect. The first wiring layer is formed over a dielectric layer and a top barrier layer is formed over the top of the first wire layer. Next, first sidewall spacers preferably composed of titanium nitride and tungsten are formed on the first wire layer sidewalls. An inter metal dielectric layer is formed over the surface. A via is then etched exposing the first wiring layer. The first titanium nitride/tungsten spacers act as an etch stop for the via etch and also increase the contact area of the wiring layers. A tungsten plug with an outer TiN barrier layer is formed filling the via contacting the first wiring layer. On top of the tungsten plug, a second wiring layer is formed also having titanium nitride and tungsten sidewall spacers. The spacers also fill in the recesses in the TiN plug barrier layer and fill in dimples in the top of the tungsten plugs.

Abstract: A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.

Abstract: A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.

Abstract: This invention provides a method of forming an attenuating phase shifting rim type photomask and an attenuating phase shifting rim type photomask for use in projection type lithographic apparatus. The photomask is formed by exposing a layer of negative photoresist through a second surface of a transparent mask substrate having a patterned layer of attenuating phase shifting material formed on a first surface of the transparent mask substrate. The exposed and developed photoresist forms a pedestal with sloping sides. A layer of opaque material is vertically anisotropically deposited on the top of the pedestal and that part of the patterned layer of attenuating phase shifting material not shaded by the pedestal. The pedestal and opaque material formed on the top of the pedestal is then removed to complete the mask.

Abstract: A polysilicon resistor structure for use within integrated circuits and a method by which the polysilicon resistor structure may be formed. A first insulating layer which is formed from a glasseous material is formed directly upon the surface of a semiconductor substrate. A polysilicon resistor is formed in contact with the first insulating layer. A second insulating layer is formed directly upon the first insulating layer and over the polysilicon resistor. The second insulating layer is formed from a silicon oxide material deposited through a Plasma Enhanced Chemical Vapor Deposition process employing silane as the silicon source material.