Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.

Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Abstract: The present teaching relates to method, system, medium, and implementations for fusing a 3D virtual model with a 2D image associated with an organ of a patient. A key-pose is determined as an approximate position and orientation of a medical instrument with respect to the patient's organ. Based on the key-pose, an overlay is generated on a 2D image of the patient's organ, acquired by the medical instrument, by projecting the 3D virtual model on to the 2D image. A pair of feature points includes a 2D feature point from the 2D image and a corresponding 3D feature point from the 3D virtual model. The 3D coordinate of the 3D feature point is determined based on the 2D coordinate of the 2D feature point. The depth of the 3D coordinate is on a line of sight of the 2D feature point and is determined so that the projection of the 3D virtual model from the depth creates an overlay approximately matching the organ observed in the 2D image.

Abstract: A resistive random access memory (RRAM) device is provided. The RRAM includes: a bottom electrode via disposed in a first dielectric layer; a bottom electrode electrically connected to the bottom electrode via and protruding upwardly from the bottom electrode via in a vertical direction, wherein the bottom electrode has a tapered shape and includes a base portion extending upwardly from a bottom surface to an interface and a tip portion extending upwardly from the interface to a top surface; a top electrode disposed in a second dielectric layer, the top electrode distanced above and vertically aligned with the bottom electrode; and a switching layer disposed between the first dielectric layer and the second dielectric layer, the switching layer enclosing the bottom electrode, wherein a conductive path between the bottom electrode and the top electrode is formed when a forming voltage is applied.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.

Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.