Patents by Inventor Chung-Liang Chu
Chung-Liang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210098342Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Chung-Liang Chu, Yu-Ruei Chen
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Patent number: 10930839Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.Type: GrantFiled: January 9, 2020Date of Patent: February 23, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 10903143Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively and disposed between the first active region and the second active region in the second direction. A length of the first gate contact structure and a length of the second gate contact structure in the second direction are less than a length of the isolation structure in the second direction.Type: GrantFiled: September 17, 2019Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen
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Patent number: 10854592Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.Type: GrantFiled: October 31, 2018Date of Patent: December 1, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Patent number: 10714466Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.Type: GrantFiled: January 23, 2019Date of Patent: July 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
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Publication number: 20200212030Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.Type: ApplicationFiled: January 23, 2019Publication date: July 2, 2020Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
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Patent number: 10660358Abstract: The present invention provides a method to convert the intrinsic sugar of a juice into indigestible oligosaccharides (such as, low-polymerization fructose and sorbitol). The present method comprises using a Zymomonas mobilis biomass and fructosyltransferase as well as pressure treatment. Taking advantage of the present method, the drawbacks of drinking juices, such as too many sugar and calorie intake can be obviated, and thereby the present invention can offer healthier option to the consumers.Type: GrantFiled: May 19, 2017Date of Patent: May 26, 2020Assignee: Food Industry Research and Development InstituteInventors: Chung-Liang Chu, Ta-Ching Cheng, Yu-Chuan Tseng
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Patent number: 10658241Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.Type: GrantFiled: December 12, 2017Date of Patent: May 19, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Publication number: 20200144483Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.Type: ApplicationFiled: December 31, 2019Publication date: May 7, 2020Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Publication number: 20200144485Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 10566520Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: GrantFiled: July 8, 2018Date of Patent: February 18, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Publication number: 20190378971Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: ApplicationFiled: July 8, 2018Publication date: December 12, 2019Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 10374006Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.Type: GrantFiled: August 6, 2018Date of Patent: August 6, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 10355048Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.Type: GrantFiled: March 13, 2018Date of Patent: July 16, 2019Assignee: United Microelectronics Corp.Inventors: Chung-Liang Chu, Yu-Ruei Chen, Hung-Yueh Chen, Yu-Ping Wang
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Publication number: 20190181046Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Publication number: 20190074272Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.Type: ApplicationFiled: October 31, 2018Publication date: March 7, 2019Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Patent number: 10153265Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.Type: GrantFiled: August 21, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Publication number: 20180110255Abstract: The present invention provides a method to convert the intrinsic sugar of a juice into indigestible oligosaccharides (such as, low-polymerization fructose and sorbitol). The present method comprises using a Zymomonas mobilis biomass and fructosyltransferase as well as pressure treatment. Taking advantage of the present method, the drawbacks of drinking juices, such as too many sugar and calorie intake can be obviated, and thereby the present invention can offer healthier option to the consumers.Type: ApplicationFiled: May 19, 2017Publication date: April 26, 2018Inventors: Chung-Liang Chu, Ta-Ching Cheng, Yu-Chuan Tseng
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Publication number: 20170365675Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Ching-Yu Chang, Ying-Chiao Wang, Hon-Huei Liu, Jyh-Shyang Jenq, Chung-Liang Chu, Yu-Ruei Chen
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Publication number: 20160235669Abstract: The present invention provides a process for preparing a water dispersion containing a high concentration of nano/submicron, hydrophobic, functional compounds. The process is carried out by using a complex stabilizer having an HLB value of about 10 to about 17, comprising lecithin and at least one non-phospholipid selected from polysorbate, sucrose ester, and polyglycerol fatty acid ester; selecting a specific weight ratio of the hydrophobic functional compounds and the stabilizer; and using homogenization technique, media milling technique, and/or centrifugal technique. The water dispersion containing a high concentration of nano/submicron, hydrophobic, functional compound produced by the process of the invention has stable dispersibility and improved bioavailability, and can be applied to the fields of foods and pharmaceuticals.Type: ApplicationFiled: April 26, 2016Publication date: August 18, 2016Inventors: RU-YIN CHEN, CHUNG-JEN CHEN, YI-JIE TSAI, JIA-JIU WU, CHIH-PING HUANG, CHUNG-LIANG CHU