Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: The disclosure provides a display panel including a first substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the first substrate and intersect each other. One of the pixel structures includes an active element, a pixel electrode, a capacitor electrode, a common electrode, and a repair pattern. The active element includes a source, a drain, and a gate. The gate is electrically connected to one of the scan lines. The source is electrically connected to one of the data lines. The pixel electrode is electrically connected to the drain of the active element. The capacitor electrode is electrically connected to the pixel electrode and extends from the drain. The common electrode overlaps the pixel electrode and the capacitor electrode. The repair pattern overlaps one of the scan lines as well as the common electrode, and the pixel electrode.

Abstract: The present invention provides a display panel having a display region and a peripheral region, and the display panel includes a plurality of pixel units including at least one inner pixel unit and at least one first peripheral pixel unit, and a shielding layer. A shape of the display region is non-rectangular. The inner pixel unit is disposed in the display region and includes at least one inner sub-pixel unit. The first peripheral pixel unit is disposed in both the display region and the peripheral region and includes at least one first peripheral sub-pixel unit. At least a part of the shielding layer is disposed in the peripheral region, and the at least a part partially overlaps the first peripheral pixel unit. A structure of the first peripheral pixel unit is different from a structure of the inner pixel unit.

Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.

Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.

Abstract: A display panel includes a substrate having a display region and a peripheral region, first and second sub pixels, first and second gate driving units. The display region includes a first area having first scan lines and first sub pixels and a second area having second scan lines and second sub pixels. A portion of the first sub pixels and a portion of the second sub pixels are respectively electrically connected to the first and second scan line. The first gate driving unit includes a first driving transistor. The second gate driving unit includes a second driving transistor. The number of the first sub pixels driven by the first gate driving unit is less than the number of the second sub pixels driven by the second gate driving unit. The channel width of the first driving transistor is less than the channel width of the second driving transistor.

Abstract: The present invention provides a display panel having a display region and a peripheral region, and the display panel includes a plurality of pixel units including at least one inner pixel unit and at least one first peripheral pixel unit, and a shielding layer. A shape of the display region is non-rectangular. The inner pixel unit is disposed in the display region and includes at least one inner sub-pixel unit. The first peripheral pixel unit is disposed in both the display region and the peripheral region and includes at least one first peripheral sub-pixel unit. At least a part of the shielding layer is disposed in the peripheral region, and the at least a part partially overlaps the first peripheral pixel unit. A structure of the first peripheral pixel unit is different from a structure of the inner pixel unit.

Abstract: An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.

Abstract: A display panel includes a substrate having a display region and a peripheral region, first and second sub pixels, first and second gate driving units. The display region includes a first area having first scan lines and first sub pixels and a second area having second scan lines and second sub pixels. A portion of the first sub pixels and a portion of the second sub pixels are respectively electrically connected to the first and second scan line. The first gate driving unit includes a first driving transistor. The second gate driving unit includes a second driving transistor. The number of the first sub pixels driven by the first gate driving unit is less than the number of the second sub pixels driven by the second gate driving unit. The channel width of the first driving transistor is less than the channel width of the second driving transistor.

Abstract: A pixel structure includes a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor includes a gate electrode formed on the first substrate, a semiconductor layer formed on the gate electrode, a first insulation layer located between the semiconductor layer and the gate electrode, and an electrode layer including a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer.

Abstract: In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

Abstract: In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

Abstract: An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.

Abstract: A pixel structure includes a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor includes a gate electrode formed on the first substrate, a semiconductor layer formed on the gate electrode, a first insulation layer located between the semiconductor layer and the gate electrode, and an electrode layer including a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer.

Abstract: A shift register and a voltage adjusting circuit and method thereof are disclosed. The voltage adjusting circuit includes a first input terminal, a second input terminal, a transistor, a first capacitor, a second capacitor, and an output terminal. The first input terminal receives a second clock signal. The second input terminal receives a fourth clock signal. The transistor has a source electrode, a drain electrode, and a gate electrode. The source electrode is coupled to ground and the gate electrode is coupled to the second input terminal. The first capacitor is coupled between the drain electrode and the first input terminal. One end of second capacitor is coupled between the first capacitor and drain electrode, and the other end of second capacitor is coupled between the second input terminal and gate electrode. The output terminal is coupled between the first capacitor and drain electrode to output an adjusted voltage.

Abstract: An active device array substrate for saving material cost includes a substrate, scan lines, data lines, a thin film transistor, a color filter layer, a transparent conductive layer, an insulating layer and a pixel electrode. The color filter layer covers and contacts the scan lines, data lines and the thin film transistor. The transparent conductive layer is disposed on the color filter layer and electrically isolated from the scan lines, the data lines and the thin film transistor by the color filter layer. The insulating layer covers the transparent conductive layer. The pixel electrode is disposed on the insulating layer and connected to the thin film transistor.

Abstract: A touch-sensing liquid crystal display is provided and includes a display panel and a backlight module. The display panel includes a transistor substrate, a liquid crystal layer and a common electrode. The liquid crystal layer is disposed on the transistor substrate. The common electrode is disposed on the liquid crystal layer. The transistor substrate includes data lines, scan lines, pixel units and a shield layer. The data lines are used to receive first signals. The scan lines are used to receive second signals. The pixel units include pixel electrodes and transistor switches, in which the transistor switches are electrically connected to the data lines, the scan lines and the pixel electrodes. The shield layer is disposed between the pixel electrodes and the transistor switches. The backlight module is disposed on the display panel, in which the liquid crystal layer is sandwiched between the shield layer and the backlight module.

Abstract: An active device array substrate for saving material cost includes a substrate, scan lines, data lines, a thin film transistor, a color filter layer, a transparent conductive layer, an insulating layer and a pixel electrode. The color filter layer covers and contacts the scan lines, data lines and the thin film transistor. The transparent conductive layer is disposed on the color filter layer and electrically isolated from the scan lines, the data lines and the thin film transistor by the color filter layer. The insulating layer covers the transparent conductive layer. The pixel electrode is disposed on the insulating layer and connected to the thin film transistor.