Patents by Inventor Chung-Ming Yu
Chung-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996481Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.Type: GrantFiled: May 17, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
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Publication number: 20240170326Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.Type: ApplicationFiled: January 25, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20240162051Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.Type: ApplicationFiled: April 27, 2023Publication date: May 16, 2024Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Patent number: 11984486Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: GrantFiled: January 23, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Publication number: 20240128324Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.Type: ApplicationFiled: November 21, 2022Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11932534Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.Type: GrantFiled: March 16, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
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Publication number: 20240088285Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
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Patent number: 11923237Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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METHOD FOR SELECTING ANTIBODY FRAGMENTS, RECOMBINANT ANTIBODIES PRODUCED THEREFROM, AND USES THEREOF
Publication number: 20230212554Abstract: Disclosed herein are methods for selecting an antibody fragment specific to an influenza virus. According to certain embodiments of the present disclosure, the influenza virus may be influenza virus type A (IAV) or influenza virus type B (IBV). Also disclosed herein are the selected antibodies, recombinant antibody produced from the selected antibodies, and the uses thereof in the diagnosis of influenza virus infection.Type: ApplicationFiled: June 7, 2021Publication date: July 6, 2023Applicant: Academia SinicaInventors: An-Suei YANG, Chung-Ming YU, Ing-Chien CHEN, Chao-Ping TUNG, Hung-Pin PENG -
Publication number: 20230168249Abstract: Disclosed herein are recombinant antibodies or the fragment thereof for detecting severe acute respiratory syndrome coronavirus (SARS-CoV). According to some embodiments, the SARS-CoV is SARS-CoV-1. According to some alternative embodiments, the SARS-CoV is SARS-CoV-2. Also disclosed herein are a kit comprising the recombinant antibodies, and a method for diagnosing the infection of SARS-CoV by using the recombinant antibody or the kit.Type: ApplicationFiled: May 4, 2021Publication date: June 1, 2023Applicant: Academia SinicaInventors: An-Suei YANG, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Ju HSU, Hung-Pin PENG, Fei-Hung HUNG
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Patent number: 11434277Abstract: Disclosed herein are methods for high-throughput screening of a virus-specific neutralizing antibody. According to certain embodiments of the present disclosure, the virus is an influenza virus. Also disclosed herein are the antibodies selected by the high-throughput screening method, and the uses thereof in the prophylaxis and/or treatment of viral infection.Type: GrantFiled: October 19, 2018Date of Patent: September 6, 2022Assignee: ACADEMIA SINICAInventors: An-Suei Yang, Ing-Chien Chen, Yi-Kai Chiu, Chung-Ming Yu, Cheng-Chung Lee, Chao-Ping Tung, Yueh-Liang Tsou, Yi-Jen Huang, Chia-Lung Lin, Hong-Sen Chen, Hwei-Jiung Wang
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Publication number: 20220213188Abstract: Provided herein is a method for treating neurodegenerative diseases, such as Alzheimer's disease (AD), by use of monoclonal antibody, which exhibits a binding affinity to Siglec-3 receptor. According to some embodiments of the present disclosure, the monoclonal antibody is capable of enhancing phagocytosis of neurotoxic peptides by immune cells thereby providing a neuroprotective effect to a subject in need thereof.Type: ApplicationFiled: September 25, 2019Publication date: July 7, 2022Applicant: Academia SinicaInventors: Shie-Liang HSIEH, Pei-Shan SUNG, Ming-Ting HUANG, An-Suei YANG, Chung-Ming YU
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Patent number: 11311922Abstract: A wire drawing process of a light storage wire includes a feeding step, a mixing step, a first drying step, a hot melt extrusion step, a first cooling step, a shaping/organizing wire step, a hot-temperature remodeling step, a stretching step, a second cooling step, a strand winding/rolling step, and a second drying step.Type: GrantFiled: February 18, 2020Date of Patent: April 26, 2022Assignee: WINN APPLIED MATERIAL INC.Inventors: Chung-Ming Yu, Shi-Wei Wang, Shih-Hao Wang
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Patent number: 11313051Abstract: A method for manufacturing a composite fabric includes the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, second drying, and weaving. The composite fabric is composed of multiple first threads and multiple second threads which are woven to the first threads. The first threads and the second threads are respectively reflective threads and glowing threads so that the composite fabric includes both features of light reflection and glowing in dark.Type: GrantFiled: September 9, 2019Date of Patent: April 26, 2022Assignee: WINN APPLIED MATERIAL INC.Inventors: Chung-Ming Yu, Shi-Wei Wang, Shih-Hao Wang
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Patent number: 11292171Abstract: The thread drawing processes include the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, and second drying. The threads made by the processes mainly use thermoplastic polyurethane particles which are easily prepared. When fabric made by the threads is attached to objects, the fabric is flat and neat.Type: GrantFiled: September 4, 2019Date of Patent: April 5, 2022Assignee: WINN APPLIED MATERIAL INC.Inventors: Chung-Ming Yu, Shi-Wei Wang, Shih-Hao Wang
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Patent number: 11242621Abstract: The adhesive thread drawing processes include the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, and second drying. The threads made by the processes are woven into fabric which has a certain level of stickiness so as to be attached onto objects without using glue and adhesive, and the fabric is flat and neat when it is attached to an object.Type: GrantFiled: September 9, 2019Date of Patent: February 8, 2022Assignee: WINN APPLIED MATERIAL INC.Inventors: Chung-Ming Yu, Shi-Wei Wang, Shih-Hao Wang
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Publication number: 20210292413Abstract: Disclosed herein is a novel monoclonal antibody exhibiting binding affinity to Siglec-3 receptor. According to the embodiment, the monoclonal antibody is capable of reversing HBV-induced immunosuppression. Accordingly, also disclosed herein are the uses thereof in the treatment and/or prophylaxis of hepatitis B virus (HBV) infection.Type: ApplicationFiled: September 25, 2018Publication date: September 23, 2021Applicant: Academia SinicaInventors: Shie-Liang HSIEH, Tsung-Yu TSAI, An-Suei YANG, Chung-Ming YU, Cheng-Yuan PENG