Patents by Inventor Chung Peng

Chung Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240181598
    Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Inventors: Tsung-Lung LAI, Cheng-Ping CHEN, Shih-Chung CHEN, Sheng-Tai PENG
  • Patent number: 12002747
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Kooi Chi Ooi, Jackson Chung Peng Kong
  • Patent number: 11996283
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
  • Patent number: 11988867
    Abstract: The present disclosure provides a package structure having a photonic integrated circuit, the package structure includes a substrate, a chip and an optical module. The chip has an optical waveguide structure and a recessed portion. The optical waveguide structure is adjacent to the recessed portion. The recessed portion faces the substrate, and the chip is engaged to the substrate by flip chip. The optical module is provided in the recessed portion of the chip.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 21, 2024
    Assignee: Molex, LLC
    Inventors: Chih-Wei Peng, Chih-Chung Hsu, Chih-Chung Wu, Zuon-Min Chuang
  • Patent number: 11975421
    Abstract: The present disclosure provides a chemical mechanical polishing system having a unitary platen. The platen includes one or more recesses within the platen to house various components for the polishing/planarization process. In one embodiment, the platen includes a first recess and a second recess. The first recess is located under the second recess. An end point detector is placed in the first recess and a detector cover may be placed in the second recess. A sealing mean is provided in a space between the end point detector and the detector cover to prevent any external or foreign materials from coming in contact with the end point detector. A fastener used for fastening the detector cover to the platen also provides addition protection to prevent foreign materials from coming in contact with components received in the recesses.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng, Rong-Long Hung
  • Publication number: 20240145368
    Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Ravindra RUDRARAJU, Vijay KASTURI
  • Publication number: 20240145365
    Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Kooi Chi OOI, Jackson Chung Peng KONG
  • Publication number: 20240145420
    Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Kooi Chi OOI, Jackson Chung Peng KONG, Jenny Shio Yin ONG
  • Publication number: 20240145450
    Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Chin Lee KUAN, Bok Eng CHEAH, Jackson Chung Peng KONG, Amit JAIN, Sameer SHEKHAR
  • Publication number: 20240136269
    Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Publication number: 20240128151
    Abstract: A package structure includes a bonding substrate, an integrated circuit, and a heat sink metal. The integrated circuit includes an active region facing the bonding substrate. The heat sink metal is located between the bonding substrate and the active region of the integrated circuit. The heat sink metal is electrically insulated with the integrated circuit.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Inventors: Chun-Yen PENG, Kuo-Bin HONG, Shih-Chen CHEN, Hao-Chung KUO
  • Patent number: 11955431
    Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Saravanan Sethuraman
  • Patent number: 11951091
    Abstract: Disclosed herein is a complex, a contrast agent and the method for treating a disease related to CXCR4 receptor. The complex is configured to bind the CXCR4 receptor, and is used as a medicament for diagnosis and treatment of cancers and other indications related to the CXCR4 receptor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 9, 2024
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Chien-Chung Hsia, Chung-Hsin Yeh, Cheng-Liang Peng, Chun-Tang Chen
  • Publication number: 20240113636
    Abstract: A dual mode charge control method includes steps of: detecting an input voltage of the resonance tank, a resonance current of the resonance tank, an output current of the load, and an output voltage of the load; performing a single-band charge control when determining a light-load condition or a no-load condition of the load according to the output current; compensating the output voltage to generate an upper threshold voltage in the single-band charge control, and acquiring a resonance voltage by calculating the resonance current by a resettable integrator; comparing the resonance voltage and the upper threshold voltage to generate a first control signal; generating a second control signal complementary to the first control signal by a pulse-width modulation duplicator; providing the first control signal and the second control signal to respectively control a first power switch and a second power switch of the resonance circuit.
    Type: Application
    Filed: January 19, 2023
    Publication date: April 4, 2024
    Inventors: Bo-Ruei PENG, Chang-Chung LIN, Yu-Jen LIN, Chia-Hsiong HUANG
  • Publication number: 20240106425
    Abstract: A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Chung-Peng HSIEH, Chih-Chiang CHANG, Yung-Chow PENG
  • Publication number: 20240104043
    Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Shailendra Singh Chauhan, Nirmala Bailur, Reza M. Zamani, Jackson Chung Peng Kong, Charuhasini Sunder Raman, Venkataramani Gopalakrishnan, Chuen Ming Tan, Sreejith Satheesakurup, Karthi Kaliswamy, Venkata Mahesh Gunnam, Yi Jen Huang, Kie Woon Lim, Dhinesh Sasidaran, Pik Shen Chee, Venkataramana Kotakonda, Kunal A. Shah, Ramesh Vankunavath, Siva Prasad Jangili Ganga, Ravali Pampala, Uma Medepalli, Tomer Savariego, Naznin Banu Wahab, Sindhusha Kodali, Manjunatha Venkatarauyappa, Surendar Jeevarathinam, Madhura Shetty, Deepak Sharma, Rohit Sharad Mahajan
  • Patent number: 11942412
    Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Tin Poay Chuah
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu