Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength.

Abstract: A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.

Abstract: Provided is a method of removing a nitride material from a semiconductor wafer. The method includes monitoring a silicon concentration level in a chemical solution. The chemical solution may include a phosphoric acid. The method includes adjusting the silicon concentration level in response to the monitoring. The method includes heating the chemical solution. The method includes applying the heated chemical solution to a wafer surface in a manner so that a temperature of the heated chemical solution is within a predefined temperature range throughout the wafer surface. The method includes etching a nitride material of the wafer using the heated chemical solution.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength.

Abstract: A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.