Patents by Inventor Chung-Shen Chen

Chung-Shen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153842
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 6876894
    Abstract: A method and apparatus for simulating the functioning of various configurations of fabrication and test equipment within a manufacturing line creates a schedule for dispatching of the production lots to the manufacturing line. Based on the product mix forecast, the product volume forecast, the predicted sales schedule, the sales confidence, the actual sales order descriptions, and the product delivery schedule, a potential product dispatch schedule is established that enables a product to be fabricated within the manufacturing line. An equipment dispatch schedule for equipment employed in fabrication and testing of the product to be fabricated is defined according to the product dispatch schedule. The potential product dispatch schedule is then simulated based on the process and test equipment model. Upon completion of the simulation, the potential product dispatch schedule is assessed for optimization.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.
    Inventors: Nai-Chiang Chen, Ta-Chin Lin, Joseph Chang, Chung-Shen Chen, Vincent Chiu
  • Patent number: D509825
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 20, 2005
    Assignee: First International Computer Inc.
    Inventor: Chung-Shen Chen