Patents by Inventor Chung-Shin Kang
Chung-Shin Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152061Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Chung-Shin KANG, Jun YANG, Hongbin JI
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Publication number: 20240126180Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.Type: ApplicationFiled: October 10, 2023Publication date: April 18, 2024Inventors: Jang Fung CHEN, Thomas L. LAIDIG, Chung-Shin KANG, Chi-Ming TSAI, Wei-Ning SHEN
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Patent number: 11934762Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.Type: GrantFiled: August 6, 2021Date of Patent: March 19, 2024Assignee: Applied Materials, Inc.Inventors: Tamer Coskun, Aidyn Kemeldinov, Chung-Shin Kang, Uwe Hollerbach, Thomas L Laidig
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Patent number: 11914305Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.Type: GrantFiled: February 18, 2020Date of Patent: February 27, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Shin Kang, Jun Yang, Hongbin Ji
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Patent number: 11906905Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.Type: GrantFiled: November 15, 2019Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Shin Kang, Yinfeng Dong, Rick R. Hung, Yao Cheng Yang, Tsaichuan Kao
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Publication number: 20230042334Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.Type: ApplicationFiled: February 18, 2020Publication date: February 9, 2023Inventors: Chung-Shin KANG, Jun YANG, Hongbin JI
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Publication number: 20230040198Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.Type: ApplicationFiled: August 6, 2021Publication date: February 9, 2023Inventors: Tamer COSKUN, Aidyn KEMELDINOV, Chung-Shin KANG, Uwe HOLLERBACH, Thomas L. LAIDIG
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Publication number: 20220365443Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.Type: ApplicationFiled: November 15, 2019Publication date: November 17, 2022Inventors: Chung-Shin KANG, Yinfeng DONG, Rick R. HUNG, Yao Cheng YANG, Tsaichuan KAO
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Publication number: 20220367438Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.Type: ApplicationFiled: September 23, 2019Publication date: November 17, 2022Inventors: Chung-Shin KANG, Thomas L. LAIDIG, Yinfeng DONG, Yao-Cheng YANG, Chen-Chien HUNG, Shivaraj Gururaj KAMALAPURA, Tsaichuan KAO
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Patent number: 11058402Abstract: Provided is a heartbeat detection signal processing method of an ultrasonic Doppler fetus monitoring device that transmits an ultrasonic wave to the abdomen of a pregnant woman and detects a fetal heartbeat rate by receiving a Doppler variation signal generated according to the fetal heartbeat.Type: GrantFiled: December 23, 2015Date of Patent: July 13, 2021Assignee: BISTOS CO., LTD.Inventors: Chung Shin Kang, Seong Ill Ko
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Patent number: 8151219Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.Type: GrantFiled: November 29, 2010Date of Patent: April 3, 2012Assignee: Cadence Design Systems, Inc.Inventors: Judy Huckabay, Weiping Fang, Chung-Shin Kang, Shiying Zhou
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Publication number: 20110167397Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.Type: ApplicationFiled: November 29, 2010Publication date: July 7, 2011Inventors: Judy Huckabay, Weiping Fang, Chung-Shin Kang, Shiying Zhou
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Patent number: 7861196Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.Type: GrantFiled: January 31, 2008Date of Patent: December 28, 2010Assignee: Cadence Design Systems, Inc.Inventors: Judy Huckabay, Weiping Fang, Chung-Shin Kang, Shiying Zhou
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Publication number: 20090199137Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Judy Huckabay, Weiping Fang, Chung-Shin Kang, Shiying Zhou