Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.

Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Abstract: A method of manufacturing a memory cell includes the following steps. A channel material is formed to contact a source line and a bit line. A ferroelectric (FE) material is formed to contact the channel material. A word line is formed to contact the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.