Patents by Inventor Chung-Ting Ko
Chung-Ting Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984485Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.Type: GrantFiled: March 3, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
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Publication number: 20240128364Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.Type: ApplicationFiled: March 27, 2023Publication date: April 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ming LUNG, Chung-Ting KO, Ting-Hsiang CHANG, Sung-En LIN, Chi On CHUI
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Patent number: 11948843Abstract: A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.Type: GrantFiled: August 6, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Ko, Sung-En Lin, Chi-On Chui
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Publication number: 20240087947Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
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Publication number: 20240079265Abstract: A method includes depositing a first material on a sidewall surface of a recess in a substrate, wherein the first material is a conductive material; after depositing the first material, depositing a second material on a bottom surface of the recess using a plasma-assisted deposition process; and after depositing the second material, removing the first material.Type: ApplicationFiled: January 9, 2023Publication date: March 7, 2024Inventors: Chung-Ting Ko, Sung-En Lin, Chi On Chui
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Patent number: 11888049Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.Type: GrantFiled: December 8, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Hong Chang, Yuan-Ching Peng, Chung-Ting Ko, Kuo-Yi Chao, Chia-Cheng Chao, You-Ting Lin, Chih-Chung Chang, Yi-Hsiu Liu, Jiun-Ming Kuo, Sung-En Lin
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Publication number: 20240021482Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Inventors: Chung-Ting Ko, Chi On Chui
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Patent number: 11855185Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: GrantFiled: March 10, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Publication number: 20230395702Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: August 2, 2023Publication date: December 7, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Patent number: 11837505Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.Type: GrantFiled: July 20, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Ko, Chi On Chui
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Publication number: 20230386930Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent semiconductor fin; recessing the isolation feature to form a recess; forming a metal-containing compound mask in the recess; depositing a stress layer over the metal-containing compound mask, such that the stress layer is in contact with a top surface of the metal-containing compound mask; and annealing the metal-containing compound mask when the stress layer is in contact with the top surface of the metal-containing compound mask.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting KO, Sung-En LIN, Chi On CHUI
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Patent number: 11830736Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.Type: GrantFiled: May 24, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Ko, Tai-Chun Huang, Chi On Chui
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Publication number: 20230377887Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Inventors: Chung-Ting Ko, Tai-Chun Huang, Chi On Chui
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Patent number: 11810824Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent semiconductor fin; recessing the isolation feature to form a recess; forming a metal-containing compound mask in the recess; depositing a stress layer over the metal-containing compound mask, such that the stress layer is in contact with a top surface of the metal-containing compound mask; and annealing the metal-containing compound mask when the stress layer is in contact with the top surface of the metal-containing compound mask.Type: GrantFiled: August 30, 2021Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Ko, Sung-En Lin, Chi On Chui
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Publication number: 20230335406Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
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Publication number: 20230282723Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure further includes a second fin structure formed over the substrate, and the second fin structure includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure further includes a dummy fin structure between the first fin structure and the second fin structure. The dummy fin structure includes a first etching stop layer between a bottom portion and a top portion.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Shao LIN, Yi-Hsiu LIU, Chih-Chung CHANG, Chung-Ting KO, Sung-En LIN
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Publication number: 20230268384Abstract: A semiconductor structure according to the present disclosure includes a base fin over a substrate, a stack of nanostructures disposed directly over the base fin, a gate structure wrapping around each of the stack of nanostructures, an isolation feature disposed over the substrate and adjacent the base fin, and a dielectric fin disposed directly on the isolation feature. The dielectric includes in a bottom portion, a middle layer over the bottom portion and a top layer over the middle layer. The bottom portion includes an outer layer and an inner layer spaced apart from the gate structure and the isolation feature by the outer layer. The middle layer is in direct contact with top surfaces of the inner layer and the outer layer. The dielectric constant of the top layer of the dielectric fin is greater than the dielectric constant of the middle layer.Type: ApplicationFiled: May 23, 2022Publication date: August 24, 2023Inventors: Tai-Jung Kuo, Zhen-Cheng Wu, Chung-Ting Ko, Sung-En Lin, Chi On Chui
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Patent number: 11728173Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: GrantFiled: September 30, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
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Patent number: 11725278Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.Type: GrantFiled: December 20, 2019Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mo Lin, Yi-Hung Lin, Jr-Hung Li, Tze-Liang Lee, Ting-Gang Chen, Chung-Ting Ko
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Publication number: 20230223304Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.Type: ApplicationFiled: May 11, 2022Publication date: July 13, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Tai-Chun Huang