Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

Abstract: A multi-piece wheel frame includes a rim and a disc. The rim includes a barrel, and an outer rim portion protruding outwardly from the barrel. The outer rim portion forms an inclined surface, and a ring edge surface connected to an outer edge of the inclined surface and cooperating with the inclined surface to form an obtuse angle. The disc is fixed to the rim, and includes a disc core, a plurality of spoke portions extending radially outwardly from the disc core, and a reinforced ring portion connected to the spoke portions and fixed to the outer rim portion. The reinforced ring portion abuts against at least one of the inclined surface and the ring edge surface.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.

Abstract: An edge narrowing method for a display panel is disclosed. The method includes the steps of providing the display panel, a grinding apparatus and a polishing apparatus; tilting the display panel so that the first substrate and a grinding member of the grinding apparatus have a first grinding angle therebetween; grinding the first substrate and the light-shielding area with the grinding apparatus while the display panel is tilted at the first grinding angle, thereby forming a first grinding end surface; stopping grinding of the first substrate and the light-shielding area when the width of the light-shielding area is between 0.35 and 1 mm; and polishing the first grinding end surface with the polishing apparatus to form a first end surface.

Abstract: A quantification method and an imaging method are disclosed, capable of quantifying the margin feature, the cysts feature, the calcifications feature, the echoic feature and the heterogenesis feature of a tumor, and capable of imaging the margin feature, the cysts feature, the calcifications feature and the heterogenesis feature of a tumor. The quantification method and the imaging method calculate the moving variance of the gray scale of each of the pixel points based on the gradient value of the gray scale of these pixel points. Then, depending on the purpose of the quantification method or the imaging method, the maximum value, the minimum value, the mean value, and the standard deviation of the moving variance of the gray scale of these pixel points are calculated, respectively. At final, with the definition of the threshold value and the imaging rule, the above features of the tumor are quantified or imaged.

Abstract: An edge narrowing method for a display panel is disclosed. The method includes the steps of providing the display panel, a grinding apparatus and a polishing apparatus; tilting the display panel so that the first substrate and a grinding member of the grinding apparatus have a first grinding angle therebetween; grinding the first substrate and the light-shielding area with the grinding apparatus while the display panel is tilted at the first grinding angle, thereby forming a first grinding end surface; stopping grinding of the first substrate and the light-shielding area when the width of the light-shielding area is between 0.35 and 1 mm; and polishing the first grinding end surface with the polishing apparatus to form a first end surface.

Abstract: An edge narrowing method for a display panel is disclosed. The display panel includes a first substrate, a second substrate, a sealant and a light-shielding area. The sealant is disposed between the first substrate and the second substrate. The light-shielding area is disposed between the first substrate and the sealant. The method includes the steps of providing the display panel, a grinding apparatus and a polishing apparatus; tilting the display panel so that the first substrate and a grinding member of the grinding apparatus have a first grinding angle therebetween; grinding the first substrate and the light-shielding area with the grinding apparatus while the display panel is tilted at the first grinding angle, thereby forming a first grinding end surface; stopping grinding of the first substrate and the light-shielding area when the width of the light-shielding area is between 0.35 and 1 mm; and polishing the first grinding end surface with the polishing apparatus to form a first end surface.

Abstract: A light emitting device includes a substrate, a patterned light-scattering layer, and an electroluminescent device. The patterned light-scattering layer is disposed on a portion of the substrate. The patterned light-scattering layer has a bottom surface in contact with the substrate, a top surface opposite to the bottom surface, and a plurality of sidewalls connecting the bottom surface and the top surface. The electroluminescent device is at least disposed on the sidewalls.

Abstract: A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure.

Abstract: A light emitting device includes a substrate, a patterned light-scattering layer, and an electroluminescent device. The patterned light-scattering layer is disposed on a portion of the substrate. The patterned light-scattering layer has a bottom surface in contact with the substrate, a top surface opposite to the bottom surface, and a plurality of sidewalls connecting the bottom surface and the top surface. The electroluminescent device is at least disposed on the sidewalls.

Abstract: A display panel includes a first substrate, a second substrate, a sealant, a plurality of spacers, and a display medium layer. The first substrate has a pixel array and a peripheral circuit. The sealant, the spacers, and the display medium layer are disposed between the first and the second substrate. The pixel array is surrounded by the sealant and located on a portion of the peripheral circuit. A multi-layer conductive wiring structure is disposed in the region of the peripheral circuit covered with the sealant. The multi-layer conductive wiring structure includes first and second conductive wirings. The second conductive wirings are connected to the pixel array via the first conductive wirings. An extending direction of the first conductive wirings is substantially different from that of the second conductive wirings. The spacers are distributed at two opposite sides of the sealant and respectively located between two adjacent first conductive wirings.

Abstract: A quantification method and an imaging method are disclosed, capable of quantifying the margin feature, the cysts feature, the calcifications feature, the echoic feature and the heterogenesis feature of a tumor, and capable of imaging the margin feature, the cysts feature, the calcifications feature and the heterogenesis feature of a tumor. The quantification method and the imaging method calculate the moving variance of the gray scale of each of the pixel points based on the gradient value of the gray scale of these pixel points. Then, depending on the purpose of the quantification method or the imaging method, the maximum value, the minimum value, the mean value, and the standard deviation of the moving variance of the gray scale of these pixel points are calculated, respectively. At final, with the definition of the threshold value and the imaging rule, the above features of the tumor are quantified or imaged.

Abstract: A display panel and a manufacture method thereof are provided. The display panel includes a first substrate, a second substrate, and a sealant. The first substrate has a top surface which includes a signal transmission module parallel to an edge of the top surface. The sealant is disposed on the top surface and parallel to the signal transmission module, which is disposed between the top surface and sealant. The sealant is made of a photo-curable material and includes an inner isolation wall, which is exposed via the signal transmission module. The second substrate is disposed on the sealant and includes an inner surface. A light-shielding structure is disposed on the inner surface and close to an edge of the inner surface. The sealant at least partially overlaps the light-shielding structure.