Abstract: A molded electronic assembly including a circuit substrate, a plurality of electronic devices, and at least one patterned heat dissipation structure is provided. The circuit substrate includes a substrate and a circuit, where the substrate has a top surface, and the circuit has a plurality of signal contacts distributed on the top surface. The electronic devices are disposed on the circuit substrate, and each of the electronic devices has a plurality of device pins connected to the signal contacts. The at least one patterned heat dissipation structure corresponds to a signal contact of the signal contacts and starts from the corresponding signal contact and extends toward a plurality of directions on the top surface of the substrate.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A multi-piece wheel frame includes a rim and a disc. The rim includes a barrel, and an outer rim portion protruding outwardly from the barrel. The outer rim portion forms an inclined surface, and a ring edge surface connected to an outer edge of the inclined surface and cooperating with the inclined surface to form an obtuse angle. The disc is fixed to the rim, and includes a disc core, a plurality of spoke portions extending radially outwardly from the disc core, and a reinforced ring portion connected to the spoke portions and fixed to the outer rim portion. The reinforced ring portion abuts against at least one of the inclined surface and the ring edge surface.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.

Abstract: A computer-implemented method of managing a thermal policy of an information handling system involves identifying a first power associated with a central processing unit (CPU) of the information handling system, identifying a first time duration of a first workload associated with the CPU, accessing a table indicating, for combinations of workload time durations and CPU power, a ramp rate and a thermal management mode, comparing the first power and the first time duration with the table to identify a first ramp rate and a first thermal management mode associated with the first power and the first time duration, and placing the CPU and a fan of the information handling system in the first thermal management mode and adjusting a fan speed of the fan based on the first ramp rate.

Abstract: Embodiments of a system, method, and memory storage device for managing performance optimization of applications executed by an Information Handling System (IHS) are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to receive telemetry data associated with an operating behavior of the IHS. Using the telemetry data, the IHS generates a profile recommendation from the received telemetry data using a machine learning (ML) service, and adjusts a core stall management mechanism of a second processor to optimize a performance of the IHS. The second processor performs at least a portion of the operating behavior of the IHS.

Abstract: A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.

Abstract: Embodiments of a system, method, and memory storage device for managing performance optimization of applications executed by an Information Handling System (IHS) are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to receive telemetry data associated with an operating behavior of the IHS. Using the telemetry data, the IHS generates a profile recommendation from the received telemetry data using a machine learning (ML) service, and adjusts a core stall management mechanism of a second processor to optimize a performance of the IHS. The second processor performs at least a portion of the operating behavior of the IHS.