Patents by Inventor Chung-Won Suh

Chung-Won Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6927437
    Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: August 9, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hyun Oh, Chung-Won Suh, Jin-Yong Seong
  • Publication number: 20040211997
    Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.
    Type: Application
    Filed: May 19, 2004
    Publication date: October 28, 2004
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang-Hyun Oh, Chung-Won Suh, Jin-Yong Seong
  • Patent number: 6773929
    Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: August 10, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hyun Oh, Chung-Won Suh, Jin-Yong Seong
  • Publication number: 20030053351
    Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.
    Type: Application
    Filed: September 13, 2002
    Publication date: March 20, 2003
    Inventors: Sang-Hyun Oh, Chung-Won Suh, Jin-Yong Seong
  • Patent number: 6338970
    Abstract: There is provided a ferroelectric capacitor of semiconductor device including a SBT ferroelectric thin film. The SBT ferroelectric thin film has double layer structure in which each layer is different in detail crystalline structure from each other fabricated at different condition of thermal treatment. The first SBT thin film is formed on the bottom electrode of capacitor by spin coating SBT precursor, baking, performing rapid thermal treatment (RTP) and furnace annealing, in turn, to form conventional crystalline grain structure. The second SBT thin film is formed on the first SBT thin film by spin coating SBT precursor with lower viscosity, baking and performing RTP, in turn, to form only crystalline nuclei. The double layer structure of the SBT ferroelectric thin film allows the SBT film to be denser and improves the surface roughness.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: January 15, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd,
    Inventor: Chung-Won Suh