Abstract: A device and method are disclosed. The device and method allow the clock signal of a wireless communication device to produce an oscillation with a 50% duty cycle. The device and method allows quick convergence to a 50% duty cycle after power up and also provides stability of the duty cycle across variations in ambient temperature and power supply fluctuations. The device includes, but is not limited to a buffer, a first inverter electrically coupled to the buffer, a second inverter electrically coupled to the first inverter, and a differential integrator, wherein a first output of the first inverter is electrically coupled to a first input of the differential integrator, wherein a second output of the second inverter is electrically coupled to a second input of the differential integrator, and wherein a third output of the differential integrator is electrically connected to the buffer.

Abstract: A device and method are disclosed. The device and method allow the clock signal of a wireless communication device to produce an oscillation with a 50% duty cycle. The device and method allows quick convergence to a 50% duty cycle after power up and also provides stability of the duty cycle across variations in ambient temperature and power supply fluctuations. The device includes, but is not limited to a buffer, a first inverter electrically coupled to the buffer, a second inverter electrically coupled to the first inverter, and a differential integrator, wherein a first output of the first inverter is electrically coupled to a first input of the differential integrator, wherein a second output of the second inverter is electrically coupled to a second input of the differential integrator, and wherein a third output of the differential integrator is electrically connected to the buffer.

Abstract: A GPS receiver and an RF GPS integrated circuit for receiving a GPS signal. The GPS integrated circuit includes a synthesizer for generating LO signals, first and second downconverters for using the LO signals for downconverting the GPS signal, and a sampler for providing in-phase and quadrature phase sampled output signals representative of the GPS signal. The synthesizer includes a multi-mode divider for providing substantially the same first LO frequency at about the midpoint of the L1 and L2 GPS lo frequencies for either of two reference frequencies. The RF GPS integrated circuit uses an entirely on-chip voltage controlled oscillator (VCO) having a resonator for generating the LO signals and an entirely on-chip filter for filtering a first intermediate frequency signal.

Abstract: A GPS/GSM receiver combination for receiving GSM and GPS signals using an RF GPS integrated circuit for downconverting the GPS signal. The GPS integrated circuit includes a synthesizer for generating LO signals, first and second downconverters for using the LO signals for downconverting the GPS signal, and a sampler for providing in-phase and quadrature phase sampled output signals representative of the GPS signal. The synthesizer includes a multi-mode divider for providing substantially the same first LO frequency at about the midpoint of the L1 and L2 GPS frequencies when either of a standard GSM reference frequency or historically common GPS reference frequency is selected. A standby mode in the integrated circuit is controlled by a power logic circuit using a power supply input as a logic control signal.

Abstract: A GPS receiver including an RF GPS integrated circuit downconverter having a standby mode controlled by a power supply input used as a logic signal. The RF GPS integrated circuit includes a synthesizer for generating LO signals, first and second downconverters for using the LO signals for downconverting the GPS signal, and a sampler for using a clock signal for providing in-phase and quadrature phase sampled output signals representative of the GPS signal. The synthesizer includes a multi-mode divider for providing substantially the same first LO frequency at about the midpoint of the L1 and L2 GPS frequencies when either of an external or internally generated reference frequency is selected. A GPS digital signal processor integrated circuit issues the logic signal and the clock signal from a single pin.

Abstract: A message system, global positioning system (GPS) receiver apparatus, and method for providing a fast time to first location fix and a low average power consumption in a GPS receiver. The message system includes a GPS base station for receiving a GPS signal and providing GPS acquisition and location information including GPS satellite visibility, health, and ephemeris; and a message system manager for transmitting a radio message signal including a wakeup call and the GPS information. A message transceiver or receiver receives the radio message signal and passes the wakeup call and GPS information to a GPS receiver having a low power standby mode. The GPS receiver awakens from the standby mode and enters an operational mode for using the GPS information for acquiring the GPS signal and deriving the first location fix. In a first embodiment, the GPS receiver initiates the first fix by requesting the message transceiver to transmit a radio request signal.

Abstract: A GPS receiver having a rapid acquisition of a GPS satellite signal when a normal operational mode is entered after a low power standby mode. The GPS receiver includes an RF section for receiving the GPS satellite signal and providing an GPS IF signal, a correlator section for providing a correlation signal for the correlation between the GPS IF signal and an internally generated replica signal, and a microprocessor section for receiving the correlation signal and calculating a geographical location of the GPS receiver. The replica signal is based upon a reference frequency from a reference oscillator and a reference time of arrival (TOA) from a timer. In order to increase acquisition speed, the microprocessor section provides the correlator section with an initial frequency adjustment and an initial TOA adjustment to correct for drift in the reference frequency during the standby mode.

Abstract: A GPS receiver having a rapid acquisition of a GPS satellite signal when a normal operational mode is entered after a low power standby mode. The GPS receiver includes an RF section for receiving the GPS satellite signal and providing an GPS IF signal, a correlator section for providing a correlation signal for the correlation between the GPS IF signal and a GPS replica signal, and a microprocessor section for receiving the correlation signal and calculating a geographical location of the GPS receiver. The GPS replica signal is based upon a reference frequency from a reference oscillator and a reference time from a timer. In the standby mode, the operation of the RF section, correlator section, and microprocessor section is inhibited while the reference oscillator and time continue to operate.

Abstract: A GPS receiver having a normal mode to receive GPS satellite signals and to provide location information, and a low power standby mode. A microprocessor system in the GPS receiver causes the GPS receiver to alternate between the normal mode and the low power standby mode in order to reduce the average power consumption in the GPS receiver. In the normal mode a GPS antenna receives GPS satellite signals, the GPS frequency downconverter converts the frequency of the GPS satellite signals to an intermediate frequency, a digital signal processing system processes the intermediate frequency to provide GPS satellite signal correlation information. The microprocessor system processes the correlation information and provides location information to a user. In the standby mode, the operating power is inhibited in the GPS antenna and the GPS frequency downconverter, the system clock is inhibited in the digital processing system, and the microprocessor clock is inhibited in the microprocessor system.

Abstract: A GPS receiver downconverter combines on a single integrated circuit, a first super-heterodyne mixer, a voltage controlled oscillator, a phase locked loop, a pair of quadrature mixers and a pair of quantizers with in-phase and quadrature-phase sampler outputs operable at twenty-five MHz and 2.5 MHz. Emitter-coupled logic and special low-voltage bipolar semiconductor technology are combined for 3.3 volt operation at under one hundred milliwatts.

Abstract: An embodiment of the present invention combines, on a single integrated circuit, an eight channel GPS receiver, a 68330-type microprocessor, a 68681-type DUART serial communications controller, an analog-to-digital converter, a real-time clock, a random access memory and a boot read-only memory. A system integration module and inter-module bus allow tri-state control of the microprocessor such that a commercially available 68332-type emulator may be used for software development.

Abstract: An embodiment of the present invention combines, on a single integrated circuit, a first bipolar transistor in a common-emitter configuration capacitively coupled to a second bipolar transistor in a common-base configuration, together with a capacitive input coupling for a single-ended input and directly-coupled collector outputs for a differential-output for driving successive differential-input and differential-output emitter-coupled transistor pairs for multiple stages of amplifier gain.

Abstract: An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

Abstract: An embodiment of the present invention is a voltage controlled oscillator (VCO) comprised of a differential pair of transistors that have respective positive feedback paths with phase-lead networks cross-coupled. Each positive feedback path on each side has two different phase-lead branches. The two phase-lead branches have the same phase differences on each side of the differential pair, in order to maintain a symmetry that improves common-mode noise rejection on a voltage control differential input. Current-steering is used to control the mixture of currents that arrive at the bases of the differential transistor pair from the respective two different phase-lead branches, and thereby changing the frequency of the VCO.

Abstract: Calibration of a vector modulator is done using a scalar detector to measure the amplitude of the RF output signal, phase shifters to adjust the relative phases of the I and Q components of the RF carrier, and variable attenuators in the I and Q modulation signal input lines to adjust the relative amplitude of the modulation signals. DC signal sources provide reference signals for the I and Q modulation inputs, carrier leak compensation signals, and calibration signals for balancing the amplitude of the I and Q modulation signals. An iterative four step calibration process is followed until no change in the results is observed. The quadrature phase error is minimized by adjusting the phase shifters. The carrier leakage is minimized by adjusting the carrier leak compensation sources to minimize RF output with the modulation inputs grounded. The amplitudes of the I and Q modulation signals are balanced by adjusting the attenuators until the output amplitudes are equal.