Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: An optical film, an optical film set, a backlight module and a display device are provided. The optical film includes a main body, plural first prism structures and plural second prism structures. The main body has a first optical surface and a second optical surface. The first prism structures are disposed on the first optical surface. Each of the first prism structures extends along a first direction. The second prism structures are disposed on the second optical surface. Each of the second prism structures extends along a second direction. The first direction is different from the second direction.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: An apparatus and a system are provided. The system includes a top plate electrode, a dielectric layer, a plurality of pixel electrode circuits, and a plurality of detection circuits. A droplet is disposed between the top plate electrode and the dielectric layer. The plurality of pixel electrode circuits are arranged in a two-dimensional array. The pixel electrode circuits in each column of the two-dimensional array are electrically connected to a respective detection circuit of the plurality of detection circuits.

Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

Abstract: An automated test mechanism includes: preparing test software capable of reading and processing a file in a general form, and making the test software support N kinds of communication interfaces, M kinds of communication protocols, and multiple commands of K kinds of instruments, wherein the general form includes an interface setting part, a communication protocol setting part, and a function list part; creating multiple general form files in the general form to support the K kinds of instruments, wherein the multiple general form files include a first file and a second file that are prepared for a first instrument and a second instrument of the multiple instruments respectively; and when performing a first test with the first instrument, choosing the first file for the first test, and when performing a second test with the second instrument, choosing the second file for the second test.

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A method of backlight control for a display panel is provided. The display panel is configured to display with a variable refresh rate in a plurality of frame periods each having a fixed period and a variable period. The method includes steps of: generating a first backlight control signal in the fixed period of a frame period; determining whether a liquid crystal (LC) transition time corresponding to the frame period ends before an end time of the variable period of the frame period; generating a second backlight control signal in the variable period of the frame period when the LC transition time ends before the end time of the variable period of the frame period; and generating a compensation backlight control signal in a next frame period according to a backlight duty cycle of the frame period.

Abstract: Provided is a dual deposition chamber apparatus for producing silicon material, the apparatus including a furnace, a cooling jacket, a deposition device, and a vacuum extraction device. The cooling jacket communicates with the furnace, defines a space above the furnace, and includes an opening communicating with the space. The deposition device includes at least one first deposition substrate and at least one second deposition substrate. The at least one first deposition substrate and the at least one second deposition substrate are arranged side by side in the space, and respectively include a first inner wall surface and a second inner wall surface inclined downwards relative to a vertical axis. An uneven area is formed on the first inner wall surface and the second inner wall surface. The vacuum extraction device communicates with the opening of the cooling jacket.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: Some embodiments include a reticle which includes first pattern features and second pattern features. A first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. The second pattern features are larger than the first pattern features. Each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. The configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. Some embodiments include photo-processing methods.

Abstract: An optical film, an optical film set, a backlight module and a display device are provided. The optical film includes a main body, plural first prism structures and plural second prism structures. The main body has a first optical surface and a second optical surface. The first prism structures are disposed on the first optical surface. Each of the first prism structures extends along a first direction. The second prism structures are disposed on the second optical surface. Each of the second prism structures extends along a second direction. The first direction is different from the second direction.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.