Patents by Inventor Chung-Yi Yu
Chung-Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030258Abstract: Doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. For example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Inventors: Chung-Liang CHENG, Sheng-Chan LI, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240030259Abstract: Doping a liner of a trench isolation structure with zinc and/or gallium reduces dark current from a photodiode. For example, the zinc and/or gallium may be deposited on a temporary oxide layer and driven into a high-k layer surrounding a deep trench isolation structure and an interface between the high-k layer and surrounding silicon. In another example, the zinc and/or gallium may be deposited on an oxide layer between the high-k layer and surrounding silicon. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Inventors: Chung-Liang CHENG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240018661Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first heating plate arranged within a processing chamber and a second heating plate arranged within the processing chamber vertically over the first heating plate. A first exhaust port is arranged within the processing chamber and a second exhaust port arranged within the processing chamber vertically over the first exhaust port. The first exhaust port is in communication with the first heating plate and is coupled to a first exhaust output. The second exhaust port is in communication with the second heating plate and is coupled to a second exhaust output. A first control element is configured to control a first exhaust pressure at the first exhaust port and a second control element is configured to control a second exhaust pressure at the second exhaust port.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20240021642Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.Type: ApplicationFiled: July 20, 2023Publication date: January 18, 2024Inventors: Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
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Publication number: 20240021719Abstract: A semiconductor device includes a substrate and a seed layer over the substrate. The seed layer includes a first seed sublayer having a first lattice structure, wherein the first seed sublayer includes AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm. The semiconductor device further includes a graded layer over the seed layer. The graded layer includes a first graded sublayer including AlGaN, having a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN having a second Al:Ga ratio. The semiconductor device further includes a two-dimensional electron gas (2-DEG) over the graded layer.Type: ApplicationFiled: July 19, 2023Publication date: January 18, 2024Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
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Publication number: 20240023445Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface is configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and is configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
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Patent number: 11862720Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).Type: GrantFiled: July 19, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
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Patent number: 11862612Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.Type: GrantFiled: December 20, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
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Patent number: 11832520Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.Type: GrantFiled: April 27, 2021Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
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Publication number: 20230378297Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu
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Publication number: 20230377946Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 11824077Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.Type: GrantFiled: November 19, 2020Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
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Patent number: 11824099Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.Type: GrantFiled: June 15, 2020Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu
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Patent number: 11814731Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.Type: GrantFiled: June 2, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20230357002Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
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Publication number: 20230361148Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
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Patent number: 11784204Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.Type: GrantFiled: October 19, 2020Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
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Publication number: 20230282612Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
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Publication number: 20230253334Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
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Patent number: 11721752Abstract: A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer.Type: GrantFiled: October 20, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee