Patents by Inventor Chung-Yu Wang

Chung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Patent number: 11996351
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Publication number: 20240169943
    Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.
    Type: Application
    Filed: July 21, 2023
    Publication date: May 23, 2024
    Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
  • Publication number: 20240169944
    Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.
    Type: Application
    Filed: October 6, 2023
    Publication date: May 23, 2024
    Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
  • Publication number: 20240165625
    Abstract: An apparatus and a system are provided. The system includes a top plate electrode, a dielectric layer, a plurality of pixel electrode circuits, and a plurality of detection circuits. A droplet is disposed between the top plate electrode and the dielectric layer. The plurality of pixel electrode circuits are arranged in a two-dimensional array. The pixel electrode circuits in each column of the two-dimensional array are electrically connected to a respective detection circuit of the plurality of detection circuits.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
  • Publication number: 20240160826
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 16, 2024
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Publication number: 20240145319
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Publication number: 20240136251
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Publication number: 20240129012
    Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 18, 2024
    Inventors: Jing-Yao XU, Chung-Ting HUNG, Chun-Yuan WANG, Chu-Yu TANG, Yi-Chih LO, Yu-Chen ZHAO, Chih-Tsung TSENG
  • Patent number: 11955405
    Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen Yu Wang, Chung-Jung Wu, Sheng-Tsung Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20240113201
    Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Ching WANG, Wei-Yang LEE, Bo-Yu LAI, Chung-I YANG, Sung-En LIN
  • Patent number: 11929331
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10721190
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a sequence to sequence to classification model for generating recommended messages. A messaging system generates, using a sequence to sequence encoder, an embedding vector from a message being transmitted as part of a communication session, the sequence to sequence encoder having been trained based on historical message data that includes messages transmitted between users of the messaging system. The messaging system determines, based on the embedding vector, a set of candidate responses for replying to the first message, the set of candidate responses being a subset of a set of available responses. The messaging system selects, from the set of candidate responses, a set of recommended responses to the first message, and causes the set of recommended responses to be presented by a client device of a recipient user of the first message.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bing Zhao, Jeffrey William Pasternack, Nandeesh Channabasappa Rajashekar, Nimesh Madhavan Chakravarthi, Chung Yu Wang, Arpit Dhariwal
  • Publication number: 20200044990
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a sequence to sequence to classification model for generating recommended messages. A messaging system generates, using a sequence to sequence encoder, an embedding vector from a message being transmitted as part of a communication session, the sequence to sequence encoder having been trained based on historical message data that includes messages transmitted between users of the messaging system. The messaging system determines, based on the embedding vector, a set of candidate responses for replying to the first message, the set of candidate responses being a subset of a set of available responses. The messaging system selects, from the set of candidate responses, a set of recommended responses to the first message, and causes the set of recommended responses to be presented by a client device of a recipient user of the first message.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Bing Zhao, Jeffrey William Pasternack, Nandeesh Channabasappa Rajashekar, Nimesh Madhavan Chakravarthi, Chung Yu Wang, Arpit Dhariwal
  • Patent number: 10269731
    Abstract: Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Kung-Chen Yeh, Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 9362474
    Abstract: A light-emitting device (LED) package component includes a carrier wafer. The carrier wafer includes a first through-substrate via (TSV) configured to electrically connecting features on opposite sides of the carrier wafer. A light-emitting device (LED) is bonded onto the carrier wafer. The LED are electrically connected to the first TSV. A conductive thermal interface material (TIM) is located between, and adjoining, the first TSV and the LED.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 7, 2016
    Assignee: EPISTAR CORPORATION
    Inventor: Chung Yu Wang
  • Patent number: 9343505
    Abstract: An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 17, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Wei Ku, Chung Yu Wang, Yu-Sheng Tang, Hsin-Hung Chen, Hao-Yu Yang, Ching-Yi Chen, Hsiao-Wen Lee, Chi Xiang Tseng, Sheng-Shin Guo, Tien-Min Lin, Shang-Yu Tsai
  • Patent number: 9337063
    Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9337096
    Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin
  • Patent number: 9136211
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang