Abstract: A voltage-controlled oscillator comprises a variable inductor, a negative impedance circuit, an operating voltage source and a ground point. The variable inductor comprises a transformer and a transistor switch, the transformer comprising a primary side coil and a secondary side coil, the primary side coil comprising a first coil and a second coil, and the secondary side coil comprising a third coil and a fourth coil. The transistor switch is connected in parallel with the primary side coil to adjust an inductance value of the variable inductor based on a gate voltage. The negative impedance circuit is connected in parallel with the secondary side coil to compensate the power consumption of the voltage-controlled oscillator during oscillation. The operating voltage source is electrically connected between the third coil and the fourth coil, and the ground point is electrically connected between the first coil and the second coil.

Abstract: The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.

Abstract: The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.

Abstract: A Pseudo Bipolar Junction Transistor(Pseudo-BJT) based retinal focal-plane sensing system is an instant image sensing and front-end processing system with the advantages of high dynamic range and instant image processing. In addition, the system proposes a Pseudo-BJT based retinal focal-plane sensor with adaptive current Schmitt trigger and smoothing network for applying a new Pseudo-BJT circuit structure to mimic parts of functions of the cells in the outer plexiform layer of the real retina. It is suitable to resolve the existing technical drawbacks performing major functions in optical image detecting circuits, such as image recognition, image tracing, robot vision, bar-code/character readers, etc.

Abstract: The invention is a biochemical sensing device, including a photodiode capable of sensing the light generated by the reaction made by a specific compound, a specific enzyme, and a luminol as well as converting the optical signal into a current signal. Also, there is a current/voltage converting circuit capable of converting the current signal into an analog voltage signal. In turn, the analog voltage signal can be converted into a digital voltage signal through an analog/digital converter. Finally, by using an electronic device, the digital voltage signal can be received and analyzed, and through the analysis, the amount of the specific compound can be measured. The device of the invention can provide a simple real-time medical assay that can be performed in massive amount. For this reason, the drawbacks of a conventional spectrum analysis instrument of being bulky and expensive can be improved.

Abstract: A Pseudo Bipolar Junction Transistor(Pseudo-BJT) based retinal focal-plane sensing system is an instant image sensing and front-end processing system with the advantages of high dynamic range and instant image processing. In addition, the system proposes a Pseudo-BJT based retinal focal-plane sensor with adaptive current Schmitt trigger and smoothing network for applying a new Pseudo-BJT circuit structure to mimic parts of functions of the cells in the outer plexiform layer of the real retina. It is suitable to resolve the existing technical drawbacks performing major functions in optical image detecting circuits, such as image recognition, image tracing, robot vision, bar-code/character readers, etc.

Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract: Dispersion is measured for an end-to-end link using two carrier wavelengths with a phase-synchronized signal modulated on each, and a single receiver that detects the BER of the combined fields. The power ratio of the two fields is chosen such that the weaker field modulates the eye of the stronger field, leading to slight periodic eye closure BER(&tgr;)≅BER(&tgr;+TB) whenever the relative group delay changes by the bit period TB. The magnitude of the relative group delay can therefore be inferred from the undulated BER response as a function of the wavelength detuning. A fit function is selected for the group delay response and the dispersion parameter D and dispersion slope S are calculated from this fit function after the function parameters are determined.

Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract: A method of equalizing the channels of a WDM link comprises identifying an error threshold level BERFail for the BER defined for each signal S(j) in accordance with the channel rate, and determining the attenuation A(j) of, for example, the power P(j) of each signal S(j) transmitted over the WDM link. The transmitter powers are adjusted taking into account the attenuations determined for all channels. The attenuation A(j) for channel (j) is determined by first setting the power P(j) of all signals S(j) to a maximum PMax, attenuating the power P(j) of channel (j) until the BER reaches the threshold value BERFail, measuring the power corresponding to the BERFail for that channel, and calculating the difference between the PMax and P(j)Fail. The transmitter powers are then set according to the relationship P(j)=PMax−&eegr;(A(j)−AMin), where &eegr; is 0.8 for a system with 3-4 channels.

Abstract: A method of equalizing the channels of a WDM link comprises identifying an error threshold level BER.sub.Fail for the BER defined for each signal S(j) in accordance with the channel rate, and determining the attenuation A(j) of, for example, the power P(j) of each signal S(j) transmitted over the WDM link. The transmitter powers are adjusted taking into account the attenuations determined for all channels. The attenuation A(j) for channel (j) is determined by first setting the power P(j) of all signals S(j) to a maximum P.sub.Max, attenuating the power P(j) of channel (j) until the BER reaches the threshold value BER.sub.Fail, measuring the power corresponding to the BER.sub.Fail for that channel, and calculating the difference between the P.sub.Max and P(j).sub.Fail. The transmitter powers are then set according to the relationship P(j)=P.sub.Max -.eta.(A(j)-A.sub.Min), where .eta. is 0.8 for a system with 3-4 channels.

Abstract: A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.

Abstract: An external adapter circuitry is plugged into the printer port of a host computer to provide the utility of computer telephony for the host computer. The circuitry is housed in a compact box which is about the size of a common parallel port connector. The circuitry consists of a telephone line interface for receiving and sending signals from/to the telephone line; a printer port interface for sending data to and receiving data from the host computer; a couple of registers for latching signal-in and signal-out; a A/D converter for converting analog signals to digital signals; and a D/A converter for converting digitized signals to analog signals. More specially, the electricity of the entire circuitry is supplied from a signal-to-power converter which obtains voltages from the printer port. Therefore, the external adapter circuitry does not need a power line for external power supply.

Abstract: A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.

Abstract: The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.

Abstract: The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

Abstract: A true type single-phase shift circuit including a pair of PMOS transistors, a pair of NMOS transistors, a pair of first-type MOS transistors and one second-type transistor. The source terminals of the two PMOS transistors are both coupled to a first electric potential, the gate terminal of one PMOS transistor is coupled to a data signal, and the gate terminal of the second PMOS transistor is connected between the two first-type MOS transistors. The source terminals of the two NMOS transistors are both coupled to a second electric potential; the gate terminal of one NMOS transitors is coupled to the data signal and the gate of the second NMOS transistor is connected between the two first-type MOS transistors. The two first type MOS transistors are serially connected between the drain terminals of one of the two PMOS transistors and the drain terminal of one of the two NMOS transistors. Each gate terminal of the two first type MOS transistors is coupled to a clock pulse signal.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.

Abstract: A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.