Patents by Inventor Chung-Ji Lu
Chung-Ji Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138359Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: August 31, 2020Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20200394355Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10762269Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20190325104Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10339248Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: GrantFiled: December 20, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20180113973Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 9852249Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: GrantFiled: July 24, 2013Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 8942053Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.Type: GrantFiled: June 27, 2012Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ji Lu, Hung-Jen Liao, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng
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Patent number: 8837250Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.Type: GrantFiled: July 20, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Cheng Xiao, Hong-Chen Cheng, Chung-Ji Lu, Cheng Hung Lee, Jung-Hsuan Chen, Li-Chun Tien
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Patent number: 8792292Abstract: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.Type: GrantFiled: March 11, 2011Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Jung-Ping Yang, Chung-Ji Lu, Derek C. Tao, Cheng Hung Lee, Hung-Jen Liao
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Publication number: 20130311964Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 8582379Abstract: A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.Type: GrantFiled: November 2, 2010Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Chih-Chieh Chiu, Chung-Ji Lu, Cheng Hung Lee
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Patent number: 8519444Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.Type: GrantFiled: September 10, 2010Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 8451669Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.Type: GrantFiled: April 10, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu-Shun Chen, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Chung-Yi Wu, Chih-Chieh Chiu
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Patent number: 8427888Abstract: A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.Type: GrantFiled: February 9, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ji Lu, Lee-Cheng Hung, Hung-Jen Liao, Hsu-Shun Chen, Hong-Chen Cheng, Chung-Yi Wu, Uppu Sharath Chandra
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Patent number: 8355277Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.Type: GrantFiled: January 19, 2011Date of Patent: January 15, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Chen Cheng, Chih-Chieh Chiu, Hsu-Shun Chen, Chung-Ji Lu, Cheng Hung Lee, Hung-Jen Liao
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Publication number: 20130010560Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.Type: ApplicationFiled: June 27, 2012Publication date: January 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ji LU, Hung-Jen LIAO, Cheng Hung LEE, Derek C. TAO, Annie-Li-Keow LUM, Hong-Chen CHENG
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Patent number: 8305831Abstract: An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.Type: GrantFiled: September 20, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Hung Lee, Chung-Yi Wu, Hsu-Shun Chen, Chung-Ji Lu
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Patent number: 8300491Abstract: A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.Type: GrantFiled: August 26, 2010Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Derek C. Tao, Annie-Li-Keow Lum, Chung-Ji Lu
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Publication number: 20120230127Abstract: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Jung-Ping Yang, Chung-Ji Lu, Derek C. Tao, Cheng Hung Lee, Hung-Jen Liao