Patents by Inventor Chunjian Yuan

Chunjian Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification system and verification method for Ethernet interface chip
    Patent number: 11868288
    Abstract: Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 9, 2024
    Assignee: SUZHOU CENTEC COMMUNICATIONS CO., LTD.
    Inventors: Yuanhan Li, Dong Wang, Chunjian Yuan, Mingda Zhang
  • Verification System and Verification Method for Ethernet Interface Chip
    Publication number: 20220374371
    Abstract: Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.
    Type: Application
    Filed: October 23, 2020
    Publication date: November 24, 2022
    Inventors: Yuanhan LI, Dong WANG, Chunjian YUAN, Mingda ZHANG
  • Method and system for accurate IPG compensation of USXGMII multi-channel
    Patent number: 10938502
    Abstract: The present invention provides a method and system for accurate IPG compensation of USXGMII multi-channel. The method comprises acquiring the length of a correspondingly deleted IPG unit between the inserted two sets of AM corresponding to each logical channel according to the working rate of a physical link, the number of distributed logical channels, the effective transmission rate corresponding to each logical channel, and the length of a set of AM inserted into each logical channel; and acquiring the data deletion interval corresponding to each logical channel, and the length of the IPG data to be deleted between the data deletion intervals according to the length of the correspondingly deleted IPG unit of each logical channel and the number of the inserted AM. The data transmission rate is enabled to be precisely matched with the bearing rate of the logical channel, thereby meeting the performance requirements.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 2, 2021
    Assignee: CENTEC NETWORKS (SU ZHOU) CO., LTD.
    Inventors: Dong Wang, Wei He, Chunjian Yuan