Patents by Inventor Chunyan E. Tian
Chunyan E. Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8421186Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.Type: GrantFiled: May 31, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Baozhen Li, Chunyan E. Tian, Chih-Chao Yang
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Publication number: 20120306048Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Baozhen Li, Chunyan E. Tian, Chih-Chao Yang
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Patent number: 8299567Abstract: Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.Type: GrantFiled: November 23, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Chunyan E Tian, Ronald Filippi, Wai-kin Li
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Publication number: 20120126363Abstract: Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Ping-Chuan Wang, Chunyan E. Tian, Ronald Filippi, Wai-ki Li
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Patent number: 7163883Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: October 27, 2003Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Patent number: 6734090Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: February 20, 2002Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20040087078Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: October 27, 2003Publication date: May 6, 2004Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20030157794Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: February 20, 2002Publication date: August 21, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel