Patents by Inventor Cing He Chen

Cing He Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230386985
    Abstract: A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu, Kuan-Yu Huang, Shu-Chia Hsu
  • Semiconductor package with heat dissipation films and manufacturing method thereof
    Patent number: 11728238
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
  • MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
    Publication number: 20220336321
    Abstract: A manufacturing method of a semiconductor package includes the following steps. An encapsulated semiconductor package is provided on a substrate. A heat dissipation sheet is cut into a plurality of heat dissipation films. The plurality of heat dissipation films are attached on the encapsulated semiconductor package, wherein the plurality of heat dissipation films jointly cover an upper surface of the encapsulated semiconductor package. A cover lid is provided on the substrate, wherein the cover lid is in contact with the plurality of heat dissipation films.
    Type: Application
    Filed: July 4, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210035884
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
  • System and method to improve package and 3DIC yield in underfill process
    Patent number: 8945983
    Abstract: A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Hsin Liu, Cing He Chen, Kewei Zuo, Chien Rhone Wang
  • System and Method to Improve Package and 3DIC Yield in Underfill Process
    Publication number: 20140183760
    Abstract: A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 3, 2014
    Inventors: Yen-Hsin Liu, Cing He Chen, Kewei Zuo, Chien Rhone Wang